A thin film transistor array panel may comprise gate lines including gate electrodes and storage electrode lines including storage electrodes that are formed on the insulating substrate, a semiconductor layer formed on the gate insulating layer covering the gate lines, data lines and drain electrodes which are formed on the gate insulating layer, the drain lines including source electrodes formed at least on the semiconductor layer and intersecting the gate lines, and the drain electrodes being separated from the data lines and opposite to the data lines with respect to the gate electrodes and including a storage capacitor conductor overlapping the storage electrodes. Pixel electrodes and common electrodes may be formed on the passivation layer for covering the semiconductor layer. The pixel electrodes and the common electrodes may be neither perpendicular to nor parallel to the data lines and may be made of opaque conductive material.