Invention Grant
- Patent Title: Method for forming a FinFET by a damascene process
- Patent Title (中): 通过镶嵌工艺形成FinFET的方法
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Application No.: US11046623Application Date: 2005-01-28
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Publication No.: US07358142B2Publication Date: 2008-04-15
- Inventor: Hee-Soo Kang , Chul Lee , Tae-Yong Kim , Dong-Gun Park , Young-Joon Ahn , Choong-Ho Lee , Sang-Yeon Han
- Applicant: Hee-Soo Kang , Chul Lee , Tae-Yong Kim , Dong-Gun Park , Young-Joon Ahn , Choong-Ho Lee , Sang-Yeon Han
- Applicant Address: KR Suown-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suown-si, Gyeonggi-do
- Agency: Marger Johnson & McCollom, P.C.
- Priority: KR10-2004-0006557 20040202
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.
Public/Granted literature
- US20050170593A1 Method for forming a FinFET by a damascene process Public/Granted day:2005-08-04
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