发明授权
US07360062B2 Method and apparatus for selecting an instruction thread for processing in a multi-thread processor
失效
一种用于在多线程处理器中选择用于处理的指令线程的方法和装置
- 专利标题: Method and apparatus for selecting an instruction thread for processing in a multi-thread processor
- 专利标题(中): 一种用于在多线程处理器中选择用于处理的指令线程的方法和装置
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申请号: US10424530申请日: 2003-04-25
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公开(公告)号: US07360062B2公开(公告)日: 2008-04-15
- 发明人: Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
- 申请人: Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: The Culbertson Group, P.C.
- 代理商 Casimer Salys; Russell D. Culbertson
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F9/40 ; G06F15/00 ; G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F9/46
摘要:
The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.