公开(公告)号：US08145885B2

公开(公告)日：2012-03-27

申请号：US12112859

申请日：2008-04-30

申请人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Balaram Sinharoy ,  John Wesley Ward, III

发明人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Balaram Sinharoy ,  John Wesley Ward, III

IPC分类号： G06F9/44 ,  G06F9/46

CPC分类号： G06F9/3851

摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.

摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。 根据规则选择每个线程的频率可以基于分配给指令线程的优先级。 随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。 该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。

公开(公告)号：US07827388B2

公开(公告)日：2010-11-02

申请号：US12044846

申请日：2008-03-07

申请人： John Wesley Ward, III ,  Minh Michelle Quy Pham ,  Ronald Nick Kalla ,  Balaram Sinharoy

发明人： John Wesley Ward, III ,  Minh Michelle Quy Pham ,  Ronald Nick Kalla ,  Balaram Sinharoy

IPC分类号： G06F9/40 ,  G06F9/42

CPC分类号： G06F9/4818 ,  G06F9/3851

摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.

摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。 除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。 然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。 然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。

公开(公告)号：US07401207B2

公开(公告)日：2008-07-15

申请号：US10424529

申请日：2003-04-25

申请人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Balaram Sinharoy ,  John Wesley Ward, III

发明人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Balaram Sinharoy ,  John Wesley Ward, III

IPC分类号： G06F9/40 ,  G06F9/44

CPC分类号： G06F9/4818 ,  G06F9/3851

摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.

摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。 除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。 然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。 然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。

公开(公告)号：US07401208B2

公开(公告)日：2008-07-15

申请号：US10424533

申请日：2003-04-25

申请人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Balaram Sinharoy ,  John Wesley Ward, III

发明人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Balaram Sinharoy ,  John Wesley Ward, III

IPC分类号： G06F9/44 ,  G06F9/46

CPC分类号： G06F9/3851

摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.

摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。 根据规则选择每个线程的频率可以基于分配给指令线程的优先级。 随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。 该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。

公开(公告)号：US07360062B2

公开(公告)日：2008-04-15

申请号：US10424530

申请日：2003-04-25

申请人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Balaram Sinharoy ,  John Wesley Ward, III

发明人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Balaram Sinharoy ,  John Wesley Ward, III

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/46

CPC分类号： G06F9/3851

摘要： The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.

摘要翻译： 可以修改SMT处理器中用于交织来自不同指令线程的指令的指令线程之间的选择以适应某些处理器事件或条件。 在每个处理器时钟周期期间，交错规则实施部件产生至少一个基本指令线程选择信号，其指示用于将指令从该特定线程传递到交错指令流中的特定指令线程。 线程选择修改由交织修改组件提供，交织修改组件基于基本线程选择信号和从各种处理器元件中的一个或多个条件或事件导出的反馈信号生成最后的线程选择信号。 该最终线程选择信号可以指示由基线程选择信号指示的相同指令线程或用于将指令传递到交错指令流的指令线程中的不同指令线程。

公开(公告)号：US20080209426A1

公开(公告)日：2008-08-28

申请号：US12112859

申请日：2008-04-30

申请人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Ballarm Sinharoy ,  John Wesley Ward, III

发明人： Ronald Nick Kalla ,  Minh Michelle Quy Pham ,  Ballarm Sinharoy ,  John Wesley Ward, III

IPC分类号： G06F9/30

CPC分类号： G06F9/3851

摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.

摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。 根据规则选择每个线程的频率可以基于分配给指令线程的优先级。 随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。 该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。

公开(公告)号：US07305586B2

公开(公告)日：2007-12-04

申请号：US10424485

申请日：2003-04-25

申请人： Richard William Doing ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  John Wesley Ward, III

发明人： Richard William Doing ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  John Wesley Ward, III

IPC分类号： G06F11/00

CPC分类号： G06F11/2236

摘要： A microprocessor includes an externally accessible port and a serial communication bus connected to the port. An execution pipeline of the processor includes a pipeline satellite circuit coupling the pipeline to the bus. The satellite enables an external agent to provide an instruction directly to the pipeline via the serial bus. A dedicated register and register satellite circuit couple the register to the communication bus. The execution pipeline can access the dedicated register during execution of the instruction. In this manner, the satellite circuits enable the external agent to access architected state. The communication bus enables access to the satellites while a system clock to the processor remains active. In one embodiment, the pipeline satellite accesses the pipeline “downstream” of the decode stage such that the set of instructions that may be “rammed” into the pipeline is not limited to the set of instructions that the decode stage can generate.

摘要翻译： 微处理器包括外部可访问端口和连接到端口的串行通信总线。 处理器的执行流水线包括将管道耦合到总线的流水线卫星电路。 该卫星使外部代理可以通过串行总线直接向管线提供指令。 专用寄存器和寄存器卫星电路将寄存器耦合到通信总线。 在执行指令期间，执行流水线可以访问专用寄存器。 以这种方式，卫星电路使外部代理能够访问架构状态。 当处理器的系统时钟保持有效时，通信总线可以访问卫星。 在一个实施例中，流水线卫星访问解码级的“下游”流水线，使得可能被“冲撞”到流水线中的指令集不限于解码级可以产生的一组指令。

公开(公告)号：US07487334B2

公开(公告)日：2009-02-03

申请号：US11050350

申请日：2005-02-03

申请人： Brian R. Konigsburg ,  Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

发明人： Brian R. Konigsburg ,  Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

IPC分类号： G06F9/34

CPC分类号： G06F9/322 ,  G06F9/382

摘要： Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to writing the branch into a Level 1 (L1) cache to provide a pre-decoded branch, and then writing the pre-decoded branch into the L1 cache. By pre-calculating matters relating to the targets of branches before the branches are written into the L1 cache, for example, by re-encoding relative branches as absolute branches, a reduction in branch redirect delay can be achieved, thus providing a substantial improvement in overall processor performance.

摘要翻译： 用于确定数据处理系统中分支目标的方法，系统和计算机程序产品。 一种用于确定数据处理系统中的分支的目标的方法包括在将分支写入级别1（L1）高速缓存之前执行与确定分支的目标有关的至少一个预计算，以提供预解码分支 ，然后将预解码的分支写入L1高速缓存。 通过在将分支写入L1高速缓存之前预先计算与分支目标相关的事项，例如通过将相关分支重新编码为绝对分支，可以实现分支重定向延迟的减少，从而提供了显着的改进 整体处理器性能。

公开(公告)号：US07269715B2

公开(公告)日：2007-09-11

申请号：US11050344

申请日：2005-02-03

申请人： Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

发明人： Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

IPC分类号： G06F9/38

CPC分类号： G06F9/3853 ,  G06F9/3802 ,  G06F9/382

摘要： An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions are part of a group including a prior set of instructions received in the instruction cache including using a history data structure, wherein the history data structure contains data regarding instructions in the prior set of instructions. Any instructions are grouped into the group with the instruction in response to a determination that the any instructions are part of the group. Instructions in the group units are dispatched to execution using the history data structure, wherein invalid instruction dispatch groupings are avoided.

摘要翻译： 一种改进的方法，装置和计算机指令，用于对在相同大小的集合中处理的指令进行分组。 在指令高速缓存中接收当前的一组指令用于调度。 确定当前指令集中的任何指令是否包括包括使用历史数据结构在指令高速缓存中接收的先前指令集的组的一部分，其中历史数据结构包含关于先前的指令的数据 一套说明 响应于确定任何指令是组的一部分，任何指令被分组到具有指令的组中。 使用历史数据结构将分组单元中的指令调度到执行，其中避免了无效指令分派分组。

公开(公告)号：US07475223B2

公开(公告)日：2009-01-06

申请号：US11050367

申请日：2005-02-03

申请人： Brian R. Konigsburg ,  Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

发明人： Brian R. Konigsburg ,  Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

IPC分类号： G06F9/00

CPC分类号： G06F9/3853 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3851

摘要： An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions prior to the set of instructions being placed in the instruction cache.

摘要翻译： 用于分组指令的改进的方法，装置和计算机指令。 接收一组指令以放置在数据处理系统中的指令高速缓存中。 指令集中的指令在被放置在指令高速缓存中的指令集之前被分组成指令的分派组合。