Multiplexer circuits that can be programmed to selectively balance the rising and falling delays through the circuits in the presence of process variations and/or variations in power levels. These multiplexer circuits can be used, for example, as programmable interconnect multiplexers in the interconnect structures of programmable logic devices (PLDs). A multiplexer circuit includes a multiplexer (e.g., driven by a plurality of interconnect lines in a PLD), a logic gate (e.g., an inverter) driven by the multiplexer, and a performance compensation circuit. The performance compensation circuit is coupled to the output terminal of the inverter, and has a compensation enable input terminal. The performance compensation circuit is coupled to adjust a trip point of the logic gate based on a value of a signal provided on the compensation enable input terminal.