利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

88 条记录 (耗时 0.023 秒)

    Method and apparatus for integrated circuit package thermo-mechanical reliability analysis
    3.
    发明授权
    Method and apparatus for integrated circuit package thermo-mechanical reliability analysis 有权
    集成电路封装热机械可靠性分析方法与装置

    公开(公告)号：US08332803B1

    公开(公告)日：2012-12-11

    申请号：US12824542

    申请日：2010-06-28

    申请人： Arifur Rahman

    发明人： Arifur Rahman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5018 ,  G06F2217/76 ,  G06F2217/80

    摘要： A method and apparatus for integrated circuit package thermo-mechanical reliability analysis are described. In some examples, a computer-implemented method of modeling stress in a packaged semiconductor device includes: selecting, using a computer, successive portions of a package layout for the semiconductor device, each of the successive portions of the package layout describing physical layout of at least one interconnect structure in the semiconductor device; for each portion of the successive portions of the package layout: (1) selecting a pre-defined layout from a library of pre-defined layouts based on the portion of the package layout; (2) obtaining pre-characterization information for the pre-defined layout that defines structural properties of the pre-defined layout; and (3) executing a modeling algorithm to determine a stress measurement for the portion of the package layout using the pre-characterization information as parametric input; and combining stress measurements for each of the successive portions of the package layout to determine a stress profile for the semiconductor device.

    摘要翻译： 描述了用于集成电路封装热机械可靠性分析的方法和装置。 在一些示例中，计算机实现的封装半导体器件中的应力建模方法包括：使用计算机选择用于半导体器件的封装布局的连续部分，封装布局的每个连续部分描述物理布局 半导体器件中的至少一个互连结构; 对于包装布局的连续部分的每个部分：（1）基于包装布局的部分从预定义布局的库中选择预定义的布局; （2）获得预定义布局的预定义信息，该预定义布局定义预定义布局的结构特性; 和（3）执行建模算法以使用预表征信息作为参数输入来确定包装布局的部分的应力测量; 以及将包装布局的每个连续部分的应力测量结合以确定半导体器件的应力分布。

    Configuration interface to stacked FPGA
    4.
    发明授权
    Configuration interface to stacked FPGA 有权
    配置接口堆叠FPGA

    公开(公告)号：US08179159B1

    公开(公告)日：2012-05-15

    申请号：US13116276

    申请日：2011-05-26

    申请人： Stephen M. Trimberger ,  Arifur Rahman

    发明人： Stephen M. Trimberger ,  Arifur Rahman

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： H03K19/17736

    摘要： A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.

    摘要翻译： 一种配置具有可配置逻辑的第一IC芯片的堆叠集成电路（“IC”）和通过芯片间触点阵列电耦合到第一IC裸片的第二IC裸片的方法包括：提供具有帧数据的帧和 第一IC芯片的帧头中的帧地址; 将帧数据存储在第一IC芯片的帧数据寄存器中; 处理帧头以确定帧目的地是否在第一IC管芯或第二IC管芯中; 响应于确定帧目的地在第二IC芯片中，通过包括第一多个芯片间接触阵列的片间帧地址总线将第二IC芯片提供帧地址; 以及通过包括第二多个芯片间接触阵列的片间帧数据总线将帧数据从第一IC芯片的帧数据寄存器写入帧目的地。

    Configuration interface to stacked FPGA
    5.
    发明授权
    Configuration interface to stacked FPGA 有权
    配置接口堆叠FPGA

    公开(公告)号：US07973555B1

    公开(公告)日：2011-07-05

    申请号：US12128459

    申请日：2008-05-28

    申请人： Stephen M. Trimberger ,  Arifur Rahman

    发明人： Stephen M. Trimberger ,  Arifur Rahman

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： H03K19/17736

    摘要： A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.

    摘要翻译： 半导体器件包括具有帧地址总线（604）的现场可编程门阵列（“FPGA”）管芯（202），帧数据总线（608）和第二集成电路（“IC”）芯片（204） 连接到FPGA模具。 芯片间帧地址总线（605）将至少在FPGA管芯和第二IC管芯之间的帧的帧地址的低位帧地址位耦合。 片间帧地址总线包括形成在FPGA管芯和第二IC管芯之间的第一多个触点（614）。 芯片间帧数据总线将帧的帧数据耦合在FPGA管芯和第二IC管芯之间。 芯片间帧数据总线包括形成在FPGA管芯和第二IC管芯之间的第二多个触点（616）。

    Floating gate field effect transistors for chemical and/or biological sensing
    6.
    发明授权
    Floating gate field effect transistors for chemical and/or biological sensing 有权
    用于化学和/或生物传感的浮栅场效应晶体管

    公开(公告)号：US07884398B2

    公开(公告)日：2011-02-08

    申请号：US12328893

    申请日：2008-12-05

    申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

    发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

    IPC分类号： H01L27/148

    CPC分类号： G01N27/4145 ,  G01N27/4148

    摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

    摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。

    Implementation of low power standby modes for integrated circuits
    9.
    发明授权
    Implementation of low power standby modes for integrated circuits 有权
    实现集成电路的低功耗待机模式

    公开(公告)号：US07498835B1

    公开(公告)日：2009-03-03

    申请号：US11268265

    申请日：2005-11-04

    申请人： Arifur Rahman ,  Sean W. Kao ,  Tim Tuan ,  Patrick J. Crotty ,  Jinsong Oliver Huang

    发明人： Arifur Rahman ,  Sean W. Kao ,  Tim Tuan ,  Patrick J. Crotty ,  Jinsong Oliver Huang

    IPC分类号： H03K19/173 ,  G11C5/14

    CPC分类号： H03K19/17772 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/148 ,  H03K19/0016 ,  H03K19/17784 ,  Y02D10/171 ,  Y02D50/20

    摘要： A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

    摘要翻译： PLD（200）包括功率管理单元（PMU 210），其响应于功率配置信号（PC）选择性地实现一个或多个不同的功率降低技术。 通过操纵PC信号，PMU可以独立地启用/禁用为CLB（101），IOB（102）和配置存储器单元（106）供电的各种电源电压电路（110,120,130）可以产生捕获信号， 导致存储在CLB的存储元件中的数据被捕获在配置存储单元中，和/或可以在电压供应电路之间切换配置存储单元的电源端子。 此外，响应于PC信号，PMU可以顺序地从多个可配置PLD部分中施加和去除电力，其中每个可配置部分可以包括任何数量的PLD资源。