Invention Grant
US07368775B2 Single transistor DRAM cell with reduced current leakage and method of manufacture
有权
具有降低的电流泄漏的单晶体管DRAM单元和制造方法
- Patent Title: Single transistor DRAM cell with reduced current leakage and method of manufacture
- Patent Title (中): 具有降低的电流泄漏的单晶体管DRAM单元和制造方法
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Application No.: US10903084Application Date: 2004-07-31
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Publication No.: US07368775B2Publication Date: 2008-05-06
- Inventor: Chih-Mu Huang , Mingchu King , Yun Chang
- Applicant: Chih-Mu Huang , Mingchu King , Yun Chang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Tung & Asscociates
- Main IPC: H01L29/72
- IPC: H01L29/72

Abstract:
A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate dielectric; forming sidewall spacer dielectric portions adjacent either side of the pass transistor to include covering a space between the pass transistor and the storage capacitor; forming a photoresist mask portion covering the pass transistor and exposing the storage capacitor; and, carrying out a P type ion implantation and drive in process to form a P doped channel region in the semiconductor substrate underlying the storage capacitor.
Public/Granted literature
- US20060022240A1 Single transistor DRAM cell with reduced current leakage and method of manufacture Public/Granted day:2006-02-02
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