发明授权
US07375552B1 Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure
有权
可编程逻辑块,具有耦合到通用互连结构的专用和可选择的查找表输出
- 专利标题: Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure
- 专利标题(中): 可编程逻辑块,具有耦合到通用互连结构的专用和可选择的查找表输出
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申请号: US11151892申请日: 2005-06-14
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公开(公告)号: US07375552B1公开(公告)日: 2008-05-20
- 发明人: Steven P. Young , Trevor J. Bauer , Manoj Chirania , Venu M. Kondapalli
- 申请人: Steven P. Young , Trevor J. Bauer , Manoj Chirania , Venu M. Kondapalli
- 申请人地址: US CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: US CA San Jose
- 代理商 Lois D. Cartier
- 主分类号: H03K19/177
- IPC分类号: H03K19/177 ; G06F7/38
摘要:
A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide either of the two LUT output signals to the general interconnect structure. An IC includes an interconnect structure (e.g., a programmable interconnect structure) and a programmable logic block coupled to the interconnect structure. The programmable logic block includes a LUT having two output terminals. A first LUT output terminal is non-programmably coupled to the interconnect structure via a first output terminal of the logic block. Both the first and the second LUT output terminals are programmably coupled to the interconnect structure via a second output terminal of the logic block, e.g., via a programmable multiplexer selecting between the two LUT output terminals.
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