发明授权
- 专利标题: System for reducing the latency of exclusive read requests in a symmetric multi-processing system
- 专利标题(中): 用于减少对称多处理系统中排他读请求的延迟的系统
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申请号: US11186333申请日: 2005-07-21
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公开(公告)号: US07376799B2公开(公告)日: 2008-05-20
- 发明人: Judson Eugene Veazey , Blaine Douglas Gaither
- 申请人: Judson Eugene Veazey , Blaine Douglas Gaither
- 申请人地址: US TX Houston
- 专利权人: Hewlett-Packard Development Company, L.P.
- 当前专利权人: Hewlett-Packard Development Company, L.P.
- 当前专利权人地址: US TX Houston
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with all of the cell boards being connected to at least one crossbar switch. The read-latency reducing system includes write-through cache memory on each of the cell boards, a modified line list on each crossbar switch having a list of cache lines that have been modified in the cache memory of each of the cell boards, and a cache coherency directory on each crossbar switch for recording the address, the status, and the location of each of the cache lines in the system. The modified line list is accessed to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line.
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