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公开(公告)号：US07861228B2
公开(公告)日：2010-12-28
申请号：US11075991
申请日：2005-03-09
IPC分类号： G01R31/28
CPC分类号： G06F11/1633 , G06F11/00 , G06F11/1438 , G06F11/1497 , G06F11/30 , G08C25/00 , H04L1/00
摘要： A method for detecting computational errors in a digital processor executing a program. The program is divided into a plurality of computation sections, and two functionally identical code segments, respectively comprising a primary segment and a secondary segment, are generated for one of the computation sections. The primary segment is executed, after which a temporal diversity timer is started. The secondary segment is then executed upon expiration of the timer. The respective results of execution of the primary segment and the secondary segment are compared after completion of execution of the secondary segment, and an error indication is provided if the respective results are not identical.
摘要翻译： 一种用于检测执行程序的数字处理器中的计算错误的方法。 该程序被分成多个计算部分，并且为一个计算部分生成分别包括主分段和次分段的两个功能相同的代码段。 执行主分段，之后开始时间分集计时器。 然后在定时器到期后执行次级段。 在次级段的执行完成之后比较主段和次段的执行的相应结果，并且如果各个结果不相同，则提供错误指示。
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公开(公告)号：US07584405B2
公开(公告)日：2009-09-01
申请号：US10726976
申请日：2003-12-03
IPC分类号： G06F11/00
CPC分类号： G06F11/1633 , G06F11/1438 , G06F11/1497 , Y10S707/99938
摘要： A method for detecting computational errors in a digital processor executing a program. Initially, the program is divided into computation segments, and source code for at least one of the segments is compiled to generate two redundant code sections. Comparison code is generated for comparing results produced by execution of the two code sections. Each of the code sections is then executed in a different computational domain to generate respective results. The results of the computation are executed to alter further flow of the program only if the respective results are identical.
摘要翻译： 一种用于检测执行程序的数字处理器中的计算错误的方法。 最初，该程序被分为计算段，并且编译至少一个段的源代码以生成两个冗余代码段。 生成比较代码来比较由两个代码段执行产生的结果。 然后在不同的计算域中执行每个代码段以产生相应的结果。 执行计算的结果仅在相应结果相同时才改变程序的进一步流程。
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公开(公告)号：US07370209B2
公开(公告)日：2008-05-06
申请号：US10354759
申请日：2003-01-30
摘要： Disclosed are systems and methods for increasing the difficulty of data sniffing. In one embodiment, a system and a method pertain to presenting information to a user via an output device, the information corresponding to characters available for identification as part of sensitive information to be entered by the user, receiving from the user via an input device identification of information other than the explicit sensitive information, the received information being indicative of the sensitive information, such that the sensitive information cannot be captured directly from the user identification through data sniffing, and interpreting the identified information to determine the sensitive information.
摘要翻译： 公开了用于增加数据嗅探难度的系统和方法。 在一个实施例中，系统和方法涉及经由输出设备向用户呈现信息，对应于可用于识别的字符的信息作为用户要输入的敏感信息的一部分，经由输入设备标识从用户接收 除了显式敏感信息之外的信息，所接收的信息指示敏感信息，使得敏感信息不能通过数据嗅探直接从用户标识中获取，并且解释识别的信息以确定敏感信息。
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4.发明授权System for reducing the latency of exclusive read requests in a symmetric multi-processing system 有权用于减少对称多处理系统中排他读请求的延迟的系统公开(公告)号：US07376799B2
公开(公告)日：2008-05-20
申请号：US11186333
申请日：2005-07-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0811 , G06F12/0813
摘要： A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with all of the cell boards being connected to at least one crossbar switch. The read-latency reducing system includes write-through cache memory on each of the cell boards, a modified line list on each crossbar switch having a list of cache lines that have been modified in the cache memory of each of the cell boards, and a cache coherency directory on each crossbar switch for recording the address, the status, and the location of each of the cache lines in the system. The modified line list is accessed to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line.
摘要翻译： 一种用于处理独占读请求的对称多处理系统。 该系统包括多个单元板，每个单元板还包括至少一个CPU和高速缓冲存储器，其中所有单元板连接到至少一个交叉开关。 读延迟减少系统包括每个单元板上的直写高速缓存存储器，每个交叉开关上的经修改的行列表具有在每个单元板的高速缓冲存储器中被修改的高速缓存线列表，以及 每个交叉开关上的缓存一致性目录，用于记录系统中每个缓存行的地址，状态和位置。 修改的行列表被访问以获得来自不包含所请求的高速缓存行的单元板的每个排他读请求的请求的高速缓存行的副本。
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公开(公告)号：US07353336B2
公开(公告)日：2008-04-01
申请号：US11075897
申请日：2005-03-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F11/108 , G06F12/0813 , G06F12/0815 , G06F2212/2542
摘要： Systems, methodologies, media, and other embodiments associated with RAID-enabling caches in multi-cell systems are described. One exemplary system embodiment includes a cell(s) configured with a RAID-enabling cache(s) that maps a visible address space to implement RAID memory. The example system may also include an additional cell(s) configured to facilitate implementing RAID memory by providing, for example, a mirroring location, a parity cell, and so on.
摘要翻译： 描述了与多小区系统中的RAID启用高速缓存相关联的系统，方法，媒体和其他实施例。 一个示例性系统实施例包括配置有启用RAID的高速缓存的单元，其映射可见地址空间以实现RAID存储器。 示例系统还可以包括被配置为通过提供例如镜像位置，奇偶校验小区等来实现RAID存储器的附加单元。
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6.发明授权Method and mechanism to use a cache to translate from a virtual bus to a physical bus 有权使用缓存从虚拟总线转换为物理总线的方法和机制公开(公告)号：US07032074B2
公开(公告)日：2006-04-18
申请号：US10814154
申请日：2004-04-01
IPC分类号： G06F12/02
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/1063
摘要： A multi-processor computer architecture reduces processing time and bus bandwidth during snoop processing. The architecture includes processors and local caches. Each local cache corresponds to one of the processors. The architecture includes one or more virtual busses coupled to the local caches and the processors, and one or more intermediary caches, where at least one intermediary cache is coupled to each virtual bus. Each intermediary cache includes a memory array and means for ensuring the intermediary cache is inclusive of associated local caches. The architecture further includes a main memory having a plurality of memory lines accessible by the processors.
摘要翻译： 多处理器计算机架构在侦听处理期间减少了处理时间和总线带宽。 该架构包括处理器和本地缓存。 每个本地缓存对应于一个处理器。 该架构包括耦合到本地高速缓存和处理器的一个或多个虚拟总线以及一个或多个中间缓存，其中至少一个中间缓存耦合到每个虚拟总线。 每个中间缓存包括存储器阵列和用于确保中间缓存包括相关联的本地高速缓存的装置。 该架构还包括具有可由处理器访问的多个存储器线的主存储器。
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7.发明授权公开(公告)号：US08677034B2
公开(公告)日：2014-03-18
申请号：US11413824
申请日：2006-04-28
CPC分类号： G06F9/5077
摘要： An I/O control system for controlling I/O devices in a multi-partition computer system. The I/O control system includes an IOP partition containing an I/O processor cell with at least one CPU executing a control program, and a plurality of standard partitions, each including a cell comprising at least one CPU executing a control program, coupled, via shared memory, to the I/O processor cell. One or more of the standard partitions becomes an enrolled partition, in communication with the I/O processor cell, in response to requesting a connection to the IOP cell. After a partition is enrolled with the I/O processor cell, I/O requests directed to the I/O devices from the enrolled partition are distributed over shared I/O resources controlled by the I/O processor cell.
摘要翻译： 一种用于在多分区计算机系统中控制I / O设备的I / O控制系统。 I / O控制系统包括IOP分区，其包含具有至少一个执行控制程序的CPU的I / O处理器单元，以及多个标准分区，每个标准分区包括执行控制程序的至少一个CPU的单元， 通过共享存储器到I / O处理器单元。 响应于请求与IOP单元的连接，一个或多个标准分区成为与I / O处理器单元通信的注册分区。 在使用I / O处理器单元注册分区之后，从注册分区引导到I / O设备的I / O请求分布在由I / O处理器单元控制的共享I / O资源上。
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公开(公告)号：US08473673B2
公开(公告)日：2013-06-25
申请号：US11166608
申请日：2005-06-24
IPC分类号： G06F13/00
CPC分类号： G06F12/023 , G06F2212/401
摘要： Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.
摘要翻译： 描述了通过选择性地控制用于将数据传送到存储器和/或从存储器传送数据的突发模式协议来（de）压缩数据的系统，方法，媒体和其他实施例，其中有助于增加存储器传送带宽的时间和位置。 。 一个示例性系统实施例包括存储器控制器，其被配置为（de）压缩存储器，以操纵与压缩数据相关联的大小数据，以及选择性地操纵将压缩数据传送到和/或从随机存取存储器传送的突发模式协议。
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9.发明授权Method and program product for avoiding cache congestion by offsetting addresses while allocating memory 有权方法和程序产品，用于通过在分配内存的同时抵消地址来避免高速缓存拥塞公开(公告)号：US07237084B2
公开(公告)日：2007-06-26
申请号：US10694302
申请日：2003-10-27
IPC分类号： G06F12/06
CPC分类号： G06F12/023 , G06F12/0802
摘要： A method of allocating memory operates to avoid overlapping hot spots in cache that can ordinarily cause cache thrashing. This method includes steps of determining a spacer size, reserving a spacer block of memory from a memory pool, and allocating memory at a location following the spacer block. In an alternative embodiment, the spacer size is determined randomly in a range of allowable spacer size. In other alternative embodiments, spacers are allocated based upon size of a previously allocated memory block.
摘要翻译： 分配存储器的方法操作以避免高速缓存中可能通常导致高速缓存颠簸的重叠热点。 该方法包括以下步骤：确定间隔物尺寸，从存储器池预留间隔块存储器，以及在间隔块后面的位置分配存储器。 在替代实施例中，间隔物尺寸在允许的间隔物尺寸的范围内随机确定。 在其他替代实施例中，基于先前分配的存储块的大小来分配间隔物。
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10.发明授权Method and mechanism to use a cache to translate from a virtual bus to a physical bus 失效使用缓存从虚拟总线转换为物理总线的方法和机制公开(公告)号：US06721848B2
公开(公告)日：2004-04-13
申请号：US09733123
申请日：2000-12-08
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/1063
摘要： Intermediary inclusive caches (IICs) translate between some number of processors using virtual addressing and a physically addressed bus. The IICs support at least one virtual bus (upper bus) connecting the IICs to central processor units (CPUs), and at least one physical bus (lower bus) connecting the IICs to a memory controller, input/output (I/O) devices and perhaps other IICs. Whenever a CPU makes a request of memory (on the upper bus), the request is looked up in an IIC. Should the data reside in the IIC, the data is provided to the CPU from the IIC through the upper bus (except in the case of coherency filters which do not cache data). If the request misses the IIC, the request is repeated on the lower bus. When the requested data comes back from the lower bus, the data is cached in the IIC and passed up to the requesting CPU through the upper bus. Whenever a snoop request comes in from the lower bus, the snooped (requested) data is looked up in the IIC. Should the snoop miss the IIC, that is the requested data is not in the IIC, the request need not be repeated on the upper bus. In the case of the snoop hit on the IIC, the snoop may be repeated on the upper bus if a coherency protocol requires.
摘要翻译： 中间包含缓存（IIC）在使用虚拟寻址和物理寻址总线的一些处理器之间进行转换。 IIC支持至少一个将IIC连接到中央处理器单元（CPU）的虚拟总线（上部总线），以及将IIC连接到存储器控制器，至少一个物理总线（下部总线），输入/输出（I / O）设备 也许其他IIC。 每当CPU发出内存请求（在上层总线上）时，请求将在IIC中查找。 如果数据位于IIC中，则数据从IIC通过上层总线提供给CPU（除了不缓存数据的一致性过滤器的情况）。 如果请求错过了IIC，请求在较低的总线上重复。 当所请求的数据从较低的总线返回时，数据被缓存在IIC中，并通过上位总线传递到请求的CPU。 每当从较低的总线进入监听请求时，在IIC中查找被窥探的（请求的）数据。 如果窥探者错过了IIC，那就是请求的数据不在IIC中，请求不需要在上层总线上重复。 在IIC上的窥探情况下，如果一致性协议需要，可以在上层总线上重复侦听。
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