- 专利标题： Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same
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申请号： US10960258申请日： 2004-10-07
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公开(公告)号： US07376915B1公开(公告)日： 2008-05-20
- 发明人: Bruce Eliot Duewer , Richard Dean Putman
- 申请人： Bruce Eliot Duewer , Richard Dean Putman
- 申请人地址： US TX Austin
- 专利权人： Cirrus Logic, Inc.
- 当前专利权人： Cirrus Logic, Inc.
- 当前专利权人地址： US TX Austin
- 代理机构： Thompson & Knight LLP
- 代理商 James J. Murphy
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.
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