A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies between nodes are made known and predictable greatly simplify the task of coordinating quiesce responses within the system. When latencies are not fixed and topologies such as open or closed bus architectures are be used a more dynamic approach is required to ensure system serialization. Adaptive quiesce logic on each node's SCE can dynamically identify the role of the node within the system and automatically configure itself to guarantee that no enabled processor within the entire system receives a quiesce indication before all processors have reached the stopped state. This is also true for systems where nodes are being concurrently added or removed during system operation. Bus states process quiesce requests. Also this method of reaching a quiesced state operates independently of differing latencies between nodes. Defined master slave end and interior nodes are used within the quiesce network.