发明授权
- 专利标题: Dual slice architectures for programmable logic devices
- 专利标题(中): 可编程逻辑器件的双切片架构
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申请号: US11446542申请日: 2006-06-02
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公开(公告)号: US07385417B1公开(公告)日: 2008-06-10
- 发明人: Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
- 申请人: Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
- 申请人地址: US OR Hillsboro
- 专利权人: Lattice Semiconductor Corporation
- 当前专利权人: Lattice Semiconductor Corporation
- 当前专利权人地址: US OR Hillsboro
- 代理机构: MacPherson Kwok Chen & Heid LLP
- 代理商 Greg J. Michelson
- 主分类号: G06F7/38
- IPC分类号: G06F7/38 ; H03K19/173
摘要:
Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.
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