Invention Grant
- Patent Title: Method to reduce soft error rate in semiconductor memory
- Patent Title (中): 降低半导体存储器软错误率的方法
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Application No.: US10919212Application Date: 2004-08-16
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Publication No.: US07389446B2Publication Date: 2008-06-17
- Inventor: Keith Krasnansky
- Applicant: Keith Krasnansky
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Steven A. Shaw; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and repairing them utilizing on-chip data storage redundancy and exchange. The program memory is protected by sensing errors and repairing damaged data by reloading it using the program stored in the boot and download memory. The data memory is selectively protected similar to the program memory, but with the added feature of regular saving to disk from which to check for accurate data in the event of corruption. In another embodiment, any or all of the soft error protection features are selectable on a global basis, a memory type basis or, in the cases of program and data memory, on a block level basis.
Public/Granted literature
- US20060036913A1 Method to reduce soft error rate in semiconductor memory Public/Granted day:2006-02-16
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