公开(公告)号：US06897681B2

公开(公告)日：2005-05-24

申请号：US10106367

申请日：2002-03-27

申请人： Keith Krasnansky

发明人： Keith Krasnansky

IPC分类号： G06F13/40 ,  H03K17/16 ,  H03K19/0175

CPC分类号： G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

摘要： The output of drivers which are used to drive the input signals to a multiplexed signal line are combined in a logic OR gate or a logic AND gate prior to connection to the input of the multiplexed line. The inactive state of drivers connected through a logic OR gate is set to 0 and the inactive state of drivers connected through a logic AND gate is set to 1. Bus contention between drivers is eliminated and the bandwidth of the multiplexed serial bus is increased because of the reduced wait time between driver transitions. Power dissipation in transition is reduced and the bus can have a programmable inactive state on a bus to allow for 1, 0 or High Z to indicate the inactive state.

摘要翻译： 用于将输入信号驱动到多路复用信号线的驱动器的输出在连接到多路复用行的输入之前被组合在逻辑或门或逻辑与门中。 通过逻辑或门连接的驱动器的无效状态被设置为0，并且通过逻辑与门连接的驱动器的不活动状态被设置为1.驱动器之间的总线争用被消除，并且多路复用串行总线的带宽因为 驱动器转换之间的等待时间缩短。 转换中的功耗降低，总线上可以有一个可编程的无效状态，以允许1,0或高Z指示不活动状态。

公开(公告)号：US07245173B2

公开(公告)日：2007-07-17

申请号：US10919137

申请日：2004-08-16

申请人： Keith Krasnansky

发明人： Keith Krasnansky

IPC分类号： H03K17/16

CPC分类号： G06F17/5063 ,  G06F2217/78 ,  H04L25/0272

摘要： A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling comprises a pair of coupled, symmetrically opposite and operatively dependent electronic signals each driven by voltages of the same magnitude, but of opposite polarity with respect to a common ground. The drive voltages of each signal are of relatively low potential as compared to the core operating voltage of present day devices. The low-voltage pair of signals tends to create offsetting fields of electromagnetic interference from the flow of current within their respective conductors which tends to minimize inductive effects (and therefore corruption of signals) in adjacent signal lines. Differential signaling replaces all or as many single-end signals as possible throughout the device resulting in relatively lower power usage as compared to present devices.

摘要翻译： 一种降低集成电路功耗的方法，包括在所述电路内广泛使用差分信号。 差分信号包括一对耦合的，对称的相对的和操作上相关的电子信号，每个电子信号由相同幅度的电压驱动，但是相对于共同的接地极性相反。 与现在的设备的核心工作电压相比，每个信号的驱动电压具有相对低的电位。 低电压信号对趋向于产生来自它们各自的导体内的电流的电磁干扰的偏移场，这倾向于最小化相邻信号线中的感应效应（因此信号的损坏）。 差分信号在整个设备上替代了尽可能多的单端信号，与现有器件相比，导致相对较低的功耗。

公开(公告)号：US20060245415A1

公开(公告)日：2006-11-02

申请号：US11116011

申请日：2005-04-27

申请人： Keith Krasnansky

发明人： Keith Krasnansky

IPC分类号： H04L12/66

CPC分类号： H04L29/06027 ,  H04L65/1069 ,  H04L65/4015

摘要： A system for adding a PC screen to a phone call comprising a phone with a “PC-Add” featured adapter and a link to an associated, PC-Add enabled PC. The PC-Add feature comprises a PC-send button, a PC-receive button and PC-Add hardware and/or software for the phone/adapter, PC and network. While on an IP phone call, a PC-Add-enabled sender presses the PC-send adapter button. While on the same call, a PC-Add-enabled receiver presses the PC-receive button on his end. The image on the sender's PC screen is sent to the receiver's PC screen. The invention comprises many embodiments, including a direct link between the phone and PC or a server supported link, transmission directly through the network or indirectly through the phones, a separate phone and PC-Add adapter combination or an integrated unit, conferencing capabilities able to display multiple sent images from multiple senders, and LAN, WAN or Internet network operation.

摘要翻译： 用于将PC屏幕添加到电话呼叫的系统，其包括具有“PC-Add”功能适配器的电话以及到相关联的启用PC的PC的链接。 PC-Add功能包括PC发送按钮，PC接收按钮和用于电话/适配器，PC和网络的PC-Add硬件和/或软件。 在IP电话呼叫时，启用PC的发送方按PC发送适配器按钮。 在同一个呼叫中，启用PC-Add的接收机按下PC端接收按钮。 发送者PC屏幕上的图像被发送到接收机的PC屏幕。 本发明包括许多实施例，包括电话和PC之间的直接链接或服务器支持的链路，直接通过网络的传输或通过电话间接的传输，单独的电话和PC-添加适配器组合或集成单元，会议能力能够 显示来自多个发送者的多个发送的图像，以及LAN，WAN或Internet网络操作。

公开(公告)号：US07389446B2

公开(公告)日：2008-06-17

申请号：US10919212

申请日：2004-08-16

申请人： Keith Krasnansky

发明人： Keith Krasnansky

IPC分类号： G06F11/00

CPC分类号： G06F11/1479 ,  G06F11/1008 ,  G06F11/1438 ,  G06F11/2084

摘要： A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and repairing them utilizing on-chip data storage redundancy and exchange. The program memory is protected by sensing errors and repairing damaged data by reloading it using the program stored in the boot and download memory. The data memory is selectively protected similar to the program memory, but with the added feature of regular saving to disk from which to check for accurate data in the event of corruption. In another embodiment, any or all of the soft error protection features are selectable on a global basis, a memory type basis or, in the cases of program and data memory, on a block level basis.

摘要翻译： 一种降低半导体存储器中软错误率的方法。 在一个实施例中，存储器被分为a）引导和下载存储器，b）程序存储器和c）数据存储器。 每个分区根据存储的数据的重要性接收保护。 启动存储器通过感测错误进行保护，并通过片上数据存储冗余和交换来修复引导存储器。 通过使用存储在引导和下载存储器中的程序通过重新加载来检测错误并修复损坏的数据来保护程序存储器。 数据存储器与程序存储器类似地有选择地被保护，但是具有定期保存到磁盘的附加功能，以便在发生损坏的情况下检查准确的数据。 在另一个实施例中，任何或所有软错误保护特征可以在全局基础上，存储器类型基础上，或者在程序和数据存储器的情况下，以块级为基础来选择。

公开(公告)号：US20070028010A1

公开(公告)日：2007-02-01

申请号：US11194350

申请日：2005-08-01

申请人： Keith Krasnansky

发明人： Keith Krasnansky

IPC分类号： G06F3/00

CPC分类号： G06F1/28

摘要： A system for tracking utilization of at least one peripheral device includes a monitoring system that is configured to provide utilization information associated with the at least one peripheral device over a sampling interval. The monitoring system provides the utilization information based on a timing signal and an input signal, the input signal indicating activation of the peripheral device. A memory system is configured to store the utilization information for at least one sampling interval. The system can be implemented as an integrated circuit, such as may be incorporated into various types of processor-based devices, including communications devices.

摘要翻译： 用于跟踪至少一个外围设备的利用的系统包括监视系统，其被配置为在采样间隔上提供与所述至少一个外围设备相关联的利用信息。 监视系统基于定时信号和输入信号提供利用信息，该输入信号指示外围设备的激活。 存储器系统被配置为存储至少一个采样间隔的利用信息。 该系统可以被实现为集成电路，诸如可以并入到各种类型的基于处理器的设备中，包括通信设备。

公开(公告)号：US20060012416A1

公开(公告)日：2006-01-19

申请号：US10894148

申请日：2004-07-19

申请人： Keith Krasnansky ,  Ronald Drafz

发明人： Keith Krasnansky ,  Ronald Drafz

IPC分类号： H03K17/16

CPC分类号： H03K19/00346

摘要： Modularized clock decoupling and signal delay management is provided for the purpose of reducing simultaneous binary signal switch-induced inductive voltage transients in lower voltage synchronous semiconductor devices. The voltage levels in low-voltage devices must be tightly maintained for proper transistor logic operations. Signal switching results in current changes on the power net of an IC. Current changes produce inductive voltage transients which propagate throughout the device and which can interfere with signal transmission and device operation. Relatively independent functioning circuits of an integrated circuit are isolated from the chip clock and each isolated circuit module is provided with its own independent, same-frequency, but slightly out-of-phase clock signal. Signal switching within any module is thus occurring out-of-phase with that of all other modules and, as a result, switch-associated voltage transients are limited to those associated with one module's circuits at a time.

公开(公告)号：US20070121604A1

公开(公告)日：2007-05-31

申请号：US11552785

申请日：2006-10-25

申请人： Praphul Chandra ,  David Lide ,  Manoj Sindhwani ,  Satish Mundra ,  Samant Kumar ,  Keith Krasnansky ,  Thomas McKinney

发明人： Praphul Chandra ,  David Lide ,  Manoj Sindhwani ,  Satish Mundra ,  Samant Kumar ,  Keith Krasnansky ,  Thomas McKinney

IPC分类号： H04L12/66

CPC分类号： H04L29/06027 ,  H04L65/1053 ,  H04L65/1059 ,  H04L65/1069 ,  H04L67/2861 ,  H04M1/2535

摘要： Disclosed above are various embodiments of VoIP communication systems that utilize low cost IP phones that rely on a centralized VoIP controller for much of the processing. Reducing the processing taking place on an IP phone may reduce the number of components that need to be on the IP phone which may result in a less expensive IP phone in terms of both cost and power. When the IP phone is embodied as a WIPP, the reduced processing may also result in more efficient communication between the WIPP and an AP. The increased communication efficiency may result in less power being used by the WIPP and effectively extend the battery life. Since a number of redundant components have been centralized, the VoIP system as a whole may be less costly. Also, centralized control may provide greater functionality and versatility in the setup and configuration of a VoIP communication system.

摘要翻译： 上面公开的是使用低成本IP电话的VoIP通信系统的各种实施例，其依赖于集中式VoIP控制器来进行大部分处理。 降低在IP电话上进行的处理可能减少需要在IP电话上的组件的数量，这可能导致成本和功耗方面较便宜的IP电话。 当IP电话被实现为WIPP时，缩减的处理也可以导致WIPP和AP之间的更有效的通信。 提高的通信效率可能导致WIPP使用的功率较少，并有效延长了电池寿命。 由于许多冗余组件已经集中，因此整个VoIP系统可能成本较低。 此外，集中控制可以在VoIP通信系统的设置和配置中提供更大的功能和多功能性。

公开(公告)号：US20060036913A1

公开(公告)日：2006-02-16

申请号：US10919212

申请日：2004-08-16

申请人： Keith Krasnansky

发明人： Keith Krasnansky

IPC分类号： G06F11/00

CPC分类号： G06F11/1479 ,  G06F11/1008 ,  G06F11/1438 ,  G06F11/2084

摘要： A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and repairing them utilizing on-chip data storage redundancy and exchange. The program memory is protected by sensing errors and repairing damaged data by reloading it using the program stored in the boot and download memory. The data memory is selectively protected similar to the program memory, but with the added feature of regular saving to disk from which to check for accurate data in the event of corruption. In another embodiment, any or all of the soft error protection features are selectable on a global basis, a memory type basis or, in the cases of program and data memory, on a block level basis.

摘要翻译： 一种降低半导体存储器中软错误率的方法。 在一个实施例中，存储器被分为a）引导和下载存储器，b）程序存储器和c）数据存储器。 每个分区根据存储的数据的重要性接收保护。 启动存储器通过感测错误进行保护，并通过片上数据存储冗余和交换来修复引导存储器。 通过使用存储在引导和下载存储器中的程序通过重新加载来检测错误并修复损坏的数据来保护程序存储器。 数据存储器与程序存储器类似地有选择地被保护，但是具有定期保存到磁盘的附加功能，以便在发生损坏的情况下检查准确的数据。 在另一个实施例中，任何或所有软错误保护特征可以在全局基础上，存储器类型基础上，或者在程序和数据存储器的情况下，以块级为基础来选择。

公开(公告)号：US20060033558A1

公开(公告)日：2006-02-16

申请号：US10919137

申请日：2004-08-16

申请人： Keith Krasnansky

发明人： Keith Krasnansky

IPC分类号： G05F1/10

CPC分类号： G06F17/5063 ,  G06F2217/78 ,  H04L25/0272

摘要： A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling comprises a pair of coupled, symmetrically opposite and operatively dependent electronic signals each driven by voltages of the same magnitude, but of opposite polarity with respect to a common ground. The drive voltages of each signal are of relatively low potential as compared to the core operating voltage of present day devices. The low-voltage pair of signals tends to create offsetting fields of electromagnetic interference from the flow of current within their respective conductors which tends to minimize inductive effects (and therefore corruption of signals) in adjacent signal lines. Differential signaling replaces all or as many single-end signals as possible throughout the device resulting in relatively lower power usage as compared to present devices.

摘要翻译： 一种降低集成电路功耗的方法，包括在所述电路内广泛使用差分信号。 差分信号包括一对耦合的，对称的相对的和操作上相关的电子信号，每个电子信号由相同幅度的电压驱动，但是相对于共同的接地极性相反。 与现在的设备的核心工作电压相比，每个信号的驱动电压具有相对低的电位。 低电压信号对趋向于产生来自它们各自的导体内的电流的电磁干扰的偏移场，这倾向于最小化相邻信号线中的感应效应（因此信号的损坏）。 差分信号在整个设备上替代了尽可能多的单端信号，与现有器件相比，导致相对较低的功耗。

公开(公告)号：US06766423B2

公开(公告)日：2004-07-20

申请号：US10043254

申请日：2002-01-14

申请人： William Mills ,  Zoran Mladenovic ,  Keith Krasnansky

发明人： William Mills ,  Zoran Mladenovic ,  Keith Krasnansky

IPC分类号： G06F1300

CPC分类号： G06F15/167 ,  G06F9/50

摘要： A message-based memory system for Digital Signal Processor (DSP) storage expansion has a shared memory device connected to a number of DSPs through a packet communication bus. Each of the DSPs has a packet bus interface interconnected to the packet bus; and a messaging unit connected to the packet bus interface. The memory device interconnected to the packet bus can provide shared memory space for the DSPs to increase the amount of memory available to each DSP. The memory device can also be utilized to provide access to common information such as shared data or shared programing that may need to be run by multiple DSPs. The DSPs and the memory device communicate through the packet bus interface by generating packetized read and write requests.

摘要翻译： 用于数字信号处理器（DSP）存储扩展的基于消息的存储器系统具有通过分组通信总线连接到多个DSP的共享存储器件。 每个DSP具有与分组总线互连的分组总线接口; 以及连接到分组总线接口的消息单元。 互连到分组总线的存储器件可以为DSP提供共享存储空间，以增加每个DSP可用的存储器的数量。 存储器件还可以用于提供对诸如可能需要由多个DSP运行的共享数据或共享编程的共同信息的访问。 DSP和存储器件通过分组式读写请求通过分组总线接口进行通信。