发明授权
- 专利标题: Method of manufacturing a semiconductor device having a dual gate structure
- 专利标题(中): 制造具有双栅结构的半导体器件的方法
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申请号: US11497972申请日: 2006-08-01
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公开(公告)号: US07390719B2公开(公告)日: 2008-06-24
- 发明人: Taek-Soo Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hag-Ju Cho , Hye-Lan Lee , Sang-Yong Kim
- 申请人: Taek-Soo Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hag-Ju Cho , Hye-Lan Lee , Sang-Yong Kim
- 申请人地址: KR
- 专利权人: Samsung Electronics, Co., Ltd.
- 当前专利权人: Samsung Electronics, Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Mills & Onello LLP
- 优先权: KR10-2005-0070499 20050802
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234
摘要:
A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.
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