发明授权
- 专利标题： Delamination reduction between vias and conductive pads
- 专利标题（中）： 通孔和导电垫之间的分层减少
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申请号： US11066705申请日： 2005-02-23
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公开(公告)号： US07394159B2公开(公告)日： 2008-07-01
- 发明人: Hideki Goto , Toshimi Kohmura
- 申请人： Hideki Goto , Toshimi Kohmura
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Schwabe, Williamson & Wyatt, P.C.
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L23/52
摘要：
Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.
公开/授权文献
- US20060186537A1 Delamination reduction between vias and conductive pads 公开/授权日：2006-08-24
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