Invention Grant
- Patent Title: High voltage tolerant output buffer
- Patent Title (中): 高耐压输出缓冲器
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Application No.: US11615680Application Date: 2006-12-22
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Publication No.: US07394291B2Publication Date: 2008-07-01
- Inventor: Rajesh Narwal , Manoj Kumar
- Applicant: Rajesh Narwal , Manoj Kumar
- Applicant Address: IN Greater Noida, UP
- Assignee: STMicroelectronics Pvt. Ltd.
- Current Assignee: STMicroelectronics Pvt. Ltd.
- Current Assignee Address: IN Greater Noida, UP
- Agency: Hogan & Hartson LLP
- Priority: IN3473/DEL/2005 20051226
- Main IPC: H03K19/0175
- IPC: H03K19/0175

Abstract:
A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.
Public/Granted literature
- US20070170955A1 HIGH VOLTAGE TOLERANT OUTPUT BUFFER Public/Granted day:2007-07-26
Information query
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