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    Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method
    1.
    发明申请
    Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method 有权
    用于数字信号的低压 - 高压电平转换器及相关集成电路，系统和方法

    公开(公告)号：US20070188193A1

    公开(公告)日：2007-08-16

    申请号：US11649746

    申请日：2007-01-03

    Applicant: Rajesh Narwal ,  Manoj Kumar

    Inventor： Rajesh Narwal ,  Manoj Kumar

    IPC: H03K19/0175

    CPC classification number: H03K19/018528

    Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

    Abstract translation: 提出了一种低电平到高电平转换器的实施例。 该转换器将芯的低电压摆幅信号转换为I / O块的高电压摆幅信号。 这种转换器对于核心和I / O电源电压差异非常大的高速应用尤其有用，例如，核心工作在0.8V，I / O工作在3.6V或更高，而没有 很少或没有静态功耗。 与传统的翻译器相比，所提出的翻译器可以提供改进的转换时间和传播延迟。 与其他这样的翻译器相比，所提出的翻译器也可以使用较少的硬件。

    HIGH VOLTAGE TOLERANT OUTPUT BUFFER
    2.
    发明申请
    HIGH VOLTAGE TOLERANT OUTPUT BUFFER 有权
    高电压容量输出缓冲器

    公开(公告)号：US20070170955A1

    公开(公告)日：2007-07-26

    申请号：US11615680

    申请日：2006-12-22

    Applicant: Rajesh Narwal ,  Manoj Kumar

    Inventor： Rajesh Narwal ,  Manoj Kumar

    IPC: H03K19/094

    CPC classification number: H03K19/00315

    Abstract: A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.

    Abstract translation: 高耐压输出缓冲器使用衬底电压控制电路来控制输出缓冲器中的晶体管的衬底上的电压。 输出缓冲器的电路使得任何晶体管的任何两个端子之间的电压不允许超过输出缓冲器的电源电压。 同时，输出缓冲器的晶体管的源极或漏极的电压不允许超过其衬底电压。 所提出的用于输出缓冲器的电路可以容忍高于其工作电压的电压。 新颖的电路使用更少的硬件并防止电路中的功耗。

    Differential input receiver with hysteresis
    3.
    发明授权
    Differential input receiver with hysteresis 有权
    具有迟滞的差分输入接收器

    公开(公告)号：US06879198B2

    公开(公告)日：2005-04-12

    申请号：US10739879

    申请日：2003-12-18

    Applicant: Manoj Kumar ,  Rajesh Narwal

    Inventor： Manoj Kumar ,  Rajesh Narwal

    IPC: H03K3/3565 ,  H03K3/037

    CPC classification number: H03K3/3565

    Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

    Abstract translation: 具有参考电压两侧的迟滞的差分输入接收器可以包括双输入单输出差分放大器，其包括连接在一起的共同端子的两个输入晶体管。 每个晶体管的控制端可以连接到差分放大器的一个输入端。 差分放大器的输出可以连接到一组级联的数字反相器/缓冲器，并且每个数字缓冲器的输出可以连接到反馈晶体管的控制端子。 反馈晶体管可以并联连接在每个输入晶体管上，使得当一个输入电压在第二输入处增加到或低于第二输入处的输入电压以下预定阈值时，反馈晶体管操作以提供正反馈以促进快速 在输出端切换动作。

    Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method
    4.
    发明授权
    Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method 有权
    用于数字信号的低压 - 高压电平转换器及相关集成电路，系统和方法

    公开(公告)号：US07999573B2

    公开(公告)日：2011-08-16

    申请号：US11649746

    申请日：2007-01-03

    Applicant: Rajesh Narwal ,  Manoj Kumar

    Inventor： Rajesh Narwal ,  Manoj Kumar

    IPC: H03K19/094

    CPC classification number: H03K19/018528

    Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

    Abstract translation: 提出了一种低电平到高电平转换器的实施例。 该转换器将芯的低电压摆幅信号转换为I / O块的高电压摆幅信号。 这种转换器对于核心和I / O电源电压差异非常大的高速应用尤其有用，例如，核心工作在0.8V，I / O工作在3.6V或更高，而没有 很少或没有静态功耗。 与传统的翻译器相比，所提出的翻译器可以提供改进的转换时间和传播延迟。 与其他这样的翻译器相比，所提出的翻译器也可以使用较少的硬件。

    High voltage tolerant output buffer
    5.
    发明授权
    High voltage tolerant output buffer 有权
    高耐压输出缓冲器

    公开(公告)号：US07394291B2

    公开(公告)日：2008-07-01

    申请号：US11615680

    申请日：2006-12-22

    Applicant: Rajesh Narwal ,  Manoj Kumar

    Inventor： Rajesh Narwal ,  Manoj Kumar

    IPC: H03K19/0175

    CPC classification number: H03K19/00315

    Abstract: A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.

    Abstract translation: 高耐压输出缓冲器使用衬底电压控制电路来控制输出缓冲器中的晶体管的衬底上的电压。 输出缓冲器的电路使得任何晶体管的任何两个端子之间的电压不允许超过输出缓冲器的电源电压。 同时，输出缓冲器的晶体管的源极或漏极的电压不允许超过其衬底电压。 所提出的用于输出缓冲器的电路可以容忍高于其工作电压的电压。 新颖的电路使用更少的硬件并防止电路中的功耗。

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