Invention Grant
US07395304B2 Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic 有权
用于在冗余形式算术中执行单周期加法或减法和比较的方法和装置

Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic
Abstract:
A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic operation is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.
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