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US07397115B2 Folding chip planar stack package 失效
折叠芯片平面堆叠封装

  • 专利标题: Folding chip planar stack package
  • 专利标题(中): 折叠芯片平面堆叠封装
  • 申请号: US11485107
    申请日: 2006-07-12
  • 公开(公告)号: US07397115B2
    公开(公告)日: 2008-07-08
  • 发明人: Ik Jae Lee
  • 申请人: Ik Jae Lee
  • 申请人地址: KR Kyoungki-go
  • 专利权人: Hynix Semiconductor Inc.
  • 当前专利权人: Hynix Semiconductor Inc.
  • 当前专利权人地址: KR Kyoungki-go
  • 代理机构: Ladas & Parry LLP
  • 优先权: KR10-2006-0028523 20060329
  • 主分类号: H01L23/02
  • IPC分类号: H01L23/02
Folding chip planar stack package
摘要:
A folding chip planar stack package is realized by employing folding chips. The folding chip planar stack package includes a substrate, first and second semiconductor chips attached to an upper surface of the substrate while being folded and spaced in parallel to each other, a bonding wire for electrically connecting the first and second semiconductor chips with the substrate, a sealing material for sealing the upper surface of the substrate including the first and second semiconductor chips and the bonding wire, and solder balls attached to a lower surface of the substrate.
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