发明授权
US07397882B2 Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion
有权
数字锁相电路能够处理以突发方式提供的输入时钟信号
- 专利标题: Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion
- 专利标题(中): 数字锁相电路能够处理以突发方式提供的输入时钟信号
-
申请号: US10671593申请日: 2003-09-29
-
公开(公告)号: US07397882B2公开(公告)日: 2008-07-08
- 发明人: Ichiro Yokokura , Yuji Obana , Hideaki Mochizuki
- 申请人: Ichiro Yokokura , Yuji Obana , Hideaki Mochizuki
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Staas & Halsey LLP
- 优先权: JP2002-284761 20020930
- 主分类号: H03D3/24
- IPC分类号: H03D3/24
摘要:
A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.