Invention Grant
US07399663B2 Embedded strain layer in thin SOI transistors and a method of forming the same
有权
薄SOI晶体管中的嵌入式应变层及其形成方法
- Patent Title: Embedded strain layer in thin SOI transistors and a method of forming the same
- Patent Title (中): 薄SOI晶体管中的嵌入式应变层及其形成方法
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Application No.: US11466572Application Date: 2006-08-23
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Publication No.: US07399663B2Publication Date: 2008-07-15
- Inventor: Jan Hoentschel , Andy Wei , Manfred Horstmann , Thorsten Kammler
- Applicant: Jan Hoentschel , Andy Wei , Manfred Horstmann , Thorsten Kammler
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102005052055 20051031
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/336
Abstract:
By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.
Public/Granted literature
- US20070096148A1 EMBEDDED STRAIN LAYER IN THIN SOI TRANSISTORS AND A METHOD OF FORMING THE SAME Public/Granted day:2007-05-03
Information query
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