发明授权
- 专利标题: Read latency control circuit
- 专利标题(中): 读延迟控制电路
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申请号: US11136712申请日: 2005-05-25
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公开(公告)号: US07404018B2公开(公告)日: 2008-07-22
- 发明人: Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
- 申请人: Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
- 申请人地址: DE Munich
- 专利权人: Infineon Technologies AG
- 当前专利权人: Infineon Technologies AG
- 当前专利权人地址: DE Munich
- 代理机构: Eschweiler & Associates LLC
- 优先权: DE102004025900 20040527
- 主分类号: G06F3/00
- IPC分类号: G06F3/00 ; G06F13/00
摘要:
The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
公开/授权文献
- US20050270852A1 Read latency control circuit 公开/授权日:2005-12-08