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公开(公告)号：US20080306723A1
公开(公告)日：2008-12-11
申请号：US12126738
申请日：2008-05-23
CPC分类号： G11C11/005 , G11C13/0004 , G11C13/0033 , G11C14/0045 , G11C14/0063
摘要： An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.
摘要翻译： 描述了在单个集成电路存储器件内提供对多种存储器类型的访问的集成电路存储器件和方法。 在各种实施例中，集成电路存储器件包括具有第一仿真存储器区域和第二仿真存储器区域的非易失性存储器阵列，以及具有接口的控制器。 存储器设备被配置为模拟第一仿真存储器类型和第二仿真存储器类型。 存储器设备还被配置为当存储器设备模拟第一仿真存储器类型时，以及当存储器件模拟第二仿真存储器类型时，在第二仿真存储器区域中，将数据存储在第一仿真存储器区域中。
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公开(公告)号：US20050219084A1
公开(公告)日：2005-10-06
申请号：US11089039
申请日：2005-03-25
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Integrated circuit with a parallel-serial converter The invention relates to an integrated circuit and method for time-offset provision of input data for a parallel-serial converter, in particular for or in a DDR semiconductor memory, having at least n input terminals at which at least n data packets are present in parallel, a delay device arranged in a manner connected downstream of the input terminals, at least some of the data packets present on the input side being output in time-offset fashion with respect to one another by said delay device, a parallel-serial converter arranged in a manner connected downstream of the delay device, which parallel-serial converter performs a conversion of the data packets that are present in parallel and are time-offset with respect to one another into an output data signal comprising the time-offset data packets in serial form, and an output terminal for outputting the output data signal.
摘要翻译： 具有并行串行转换器的集成电路技术领域本发明涉及一种用于时间偏移提供用于并行 - 串行转换器的输入数据的集成电路和方法，特别是用于或在DDR半导体存储器中的至少n个输入端子， 并行存在至少n个数据分组，延迟装置以连接在输入端子下游的方式布置，存在于输入侧的数据分组中的至少一些以相对于彼此的时间偏移方式通过所述 延迟装置，并联串行转换器，以与延迟装置下游相连的方式布置，该并行串行转换器对并行存在的并相对于彼此进行时间偏移的数据包进行转换，并将其转换为输出数据 包括串行形式的时间偏移数据分组的信号和用于输出输出数据信号的输出端。
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公开(公告)号：US06948014B2
公开(公告)日：2005-09-20
申请号：US10396966
申请日：2003-03-25
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C2207/107
摘要： Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers (2), each comprising series-connected data holding elements (3), each data holding element (3) being connected to a data input line (5), each shift register (2), upon receiving an input control signal (INP) for the shift register (2), loading the data present on the data input lines (5) into the data holding elements (3) connected thereto; each shift register (2), upon receiving an output control signal (OUTP) for the shift register (2), outputting the datum buffer-stored in the last data holding element of the shift register (2), in which case there is connected downstream of each shift register (2) a further data holding element (10), which, upon receiving an input control signal (INP) for loading the preceding shift register (2), is preloaded with the datum for the first data holding element (3-3) of the shift register (2) and, upon reception of the output control signal (OUTP) for the shift register (2), outputs said preloaded datum to an output data line (22) via a data signal driver (18) for generating a serial output data stream with unambiguous data signal states.
摘要翻译： 注册具有多个循环驱动的移位寄存器（2）的数据的并行 - 串行转换，每个包括串联连接的数据保持元件（3），每个数据保持元件（3）连接到数据输入线（5） ，每个移位寄存器（2）在接收到用于移位寄存器（2）的输入控制信号（INP）时，将存在于数据输入线（5）上的数据加载到与其连接的数据保持元件（3）中; 每个移位寄存器（2）在接收到用于移位寄存器（2）的输出控制信号（OUTP）时，输出存储在移位寄存器（2）的最后数据保持元件中的数据缓冲器，在这种情况下， 在每个移位寄存器（2）的下游具有另外的数据保持元件（10），其在接收到用于加载前一移位寄存器（2）的输入控制信号（INP）时，预先加载有用于第一数据保持元件 3），并且在接收到用于移位寄存器（2）的输出控制信号（OUTP）时，经由数据信号驱动器（18）将所述预加载的数据输出到输出数据线（22） ），用于产生具有明确数据信号状态的串行输出数据流。
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公开(公告)号：US07969806B2
公开(公告)日：2011-06-28
申请号：US12110859
申请日：2008-04-28
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G06F12/0238 , G06F12/0246 , G06F2212/1004 , G06F2212/7202 , G06F2212/7205 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0061 , G11C13/0069 , G11C2213/31 , G11C2213/32
摘要： An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.
摘要翻译： 集成电路包括存储器段，每个存储器段具有可在第一和第二状态下配置以存储数据的至少一个存储单元，以及控制存储器段的编程和擦除的控制器。 控制器将写入数据的外部存储器地址映射到已擦除存储器段的内部存储器地址，而没有存储器单元处于第一状态，使得擦除的存储器段被编写为写入数据。 当对于先前映射到具有处于第一状态的至少一个存储器单元的编程存储器段的内部存储器地址的外部存储器地址进行写访问时，控制器将外部存储器地址重新映射到擦除的存储器段的另一内部存储器地址 。 控制器识别要擦除的已编程存储器段，并且控制所识别的已编程存储器段的选择性擦除，例如不再映射到外部存储器地址的编程存储器段。
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公开(公告)号：US07583546B2
公开(公告)日：2009-09-01
申请号：US11855859
申请日：2007-09-14
IPC分类号： G11C7/00
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0076 , G11C2213/79
摘要： The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.
摘要翻译： 一种操作集成电路的方法，包括写入存储单元的步骤，该存储单元可以采取第一和第二逻辑状态，并且其中从第二逻辑状态到第一逻辑状态的改变比从第一逻辑 状态到第二逻辑状态，包括读取存储器单元的逻辑状态，根据存储单元读取的逻辑状态，将逻辑状态改变到第一逻辑状态或将其保持在第一逻辑状态，并且依赖 在待写入的逻辑状态下，将逻辑状态改变为第二逻辑状态或将其保持在第一逻辑状态。
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6.发明申请Method of Operating an Integrated Circuit, Integrated Circuit, and Memory Module 有权操作集成电路，集成电路和存储器模块的方法公开(公告)号：US20090021976A1
公开(公告)日：2009-01-22
申请号：US11778549
申请日：2007-07-16
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C5/02 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/79
摘要： A method of operating an integrated circuit is provided. The integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first input terminal and a second input terminal; a signal line being connected to the plurality of resistivity changing memory cells, the at least one resistivity changing reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. The method includes: closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first voltage and the second voltage using the voltage comparator, wherein the first voltage represents a memory state of a resistivity changing memory cell, and the second voltage is a reference voltage which represents a memory state of a resistivity changing reference cell, or vice versa.
摘要翻译： 提供一种操作集成电路的方法。 集成电路包括多个电阻率变化存储单元和至少一个电阻率变化参考单元; 电压比较器，包括第一输入端子和第二输入端子; 信号线连接到所述多个电阻率变化存储单元，所述至少一个电阻率变化参考单元和所述第二输入端子; 以及将第一输入端子连接到第二输入端子的开关元件。 该方法包括：闭合开关元件; 经由所述信号线和所述开关元件向所述第一输入端提供第一电压; 打开开关元件; 经由信号线向第二输入端提供第二电压; 以及使用所述电压比较器来比较所述第一电压和所述第二电压，其中所述第一电压表示电阻率变化存储单元的存储状态，所述第二电压是表示电阻率变化参考单元的存储状态的参考电压，或 反之亦然。
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公开(公告)号：US07215263B2
公开(公告)日：2007-05-08
申请号：US11089034
申请日：2005-03-25
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.
摘要翻译： 本发明涉及一种用于将并行数据转换为串行数据的并行数据转换器，特别是用于或在DDR半导体存储器中，具有并行存在n个数据信号的至少n个输入端，用于输出串行数据的输出端子 数据信号，连接到输入侧的输入端的可控制锁存器，连接到锁存器的输出并保持最后存在的可控制锁存器的数据信号的公共存储节点，可控旁路装置，其具有 输入，其耦合到输出侧的存储节点并且具有控制终端，通过该输入可以将存在于旁路设备的输入端的可预定状态切换到存储节点。 本发明还涉及具有这种并行 - 串行转换器的半导体存储器以及用于操作这种并行 - 串行转换器的方法。
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公开(公告)号：US20090268513A1
公开(公告)日：2009-10-29
申请号：US12111774
申请日：2008-04-29
申请人： Luca De Ambroggi , Jan Boris Philipp , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl
发明人： Luca De Ambroggi , Jan Boris Philipp , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl
CPC分类号： G11C13/0069 , G11C11/005 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2211/5641 , G11C2213/71 , G11C2213/79
摘要： A memory includes a first memory device including an array of phase changing memory cells. The first memory device is of a first memory type. The integrated circuit includes a second memory device including an array of phase changing memory cells. The second memory device is of a second memory type that is different than the first memory type. The first and second memory devices are packaged together into a single memory device.
摘要翻译： 存储器包括包括相变存储器单元的阵列的第一存储器件。 第一存储器件是第一存储器类型。 集成电路包括包括相变存储器单元的阵列的第二存储器件。 第二存储器件是与第一存储器类型不同的第二存储器类型。 第一和第二存储器件一起封装成单个存储器件。
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9.发明授权Device for driving a memory cell of a memory module by means of a charge store 失效用于通过电荷存储器驱动存储器模块的存储单元的装置公开(公告)号：US07012843B2
公开(公告)日：2006-03-14
申请号：US10180818
申请日：2002-06-26
申请人： Peter Schroegmeier , Thilo Marx , Manfred Dobler
发明人： Peter Schroegmeier , Thilo Marx , Manfred Dobler
IPC分类号： G11C7/00
CPC分类号： G11C11/4085
摘要： A device for driving a memory cell (601) of a memory module which can be operated with an external voltage (VEXT) and an operating frequency (fCLK), whereas the memory cell (601) has a capacitance (600) for storing charges and a transistor (602) for reading charges from the capacitance (600) and for writing charges to the capacitance (600), which transistor can be controlled with a control voltage (VPP), which has a charge store (614) for supplying a control voltage (VPP) which is greater than the external voltage (VEXT). The charge store (614) being able to be charged by the external voltage (VEXT), and the charging of the charge store (614) is able to be controlled by a charging control frequency (fCC) derived from the operating frequency (fCLK) of the memory module.
摘要翻译： 一种用于驱动存储器模块的存储单元（601）的装置，其可以用外部电压（V OUT）和工作频率（f CLK）操作，而 存储单元（601）具有用于存储电荷的电容（600）和用于从电容（600）读取电荷并用于向电容（600）写入电荷的晶体管（602），该晶体管可以用控制电压 （V SUB PP）具有用于提供大于外部电压（V OUT）的控制电压（V SUB PP）的电荷存储器（614） / SUB>）。 电荷存储器（614）能够被外部电压（V OUT）充电，并且电荷存储器（614）的充电能够通过充电控制频率（f < 从存储器模块的工作频率（f CLK）导出的信号（SUB> CC ）。
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公开(公告)号：US20050270852A1
公开(公告)日：2005-12-08
申请号：US11136712
申请日：2005-05-25
IPC分类号： G06F3/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译： 本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。 本发明还提供了一种用于执行该方法的相应电路装置。
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