发明授权
- 专利标题: Method to increase coupling ratio of source to floating gate in split-gate flash
- 专利标题(中): 提高分流栅闪光时源极与浮栅耦合比的方法
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申请号: US11122726申请日: 2005-05-05
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公开(公告)号: US07417278B2公开(公告)日: 2008-08-26
- 发明人: Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
- 申请人: Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Thomas, Kayden, Horstemeyer & Risley
- 主分类号: H01L29/788
- IPC分类号: H01L29/788
摘要:
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.
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