发明授权
US07418688B2 Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit
有权
集成电路的路由分析方法,逻辑综合方法和电路划分方法
- 专利标题: Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit
- 专利标题(中): 集成电路的路由分析方法,逻辑综合方法和电路划分方法
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申请号: US11111720申请日: 2005-04-22
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公开(公告)号: US07418688B2公开(公告)日: 2008-08-26
- 发明人: Toshiyuki Sadakane , Ken Saito , Yoshio Inoue
- 申请人: Toshiyuki Sadakane , Ken Saito , Yoshio Inoue
- 申请人地址: JP Chiyoda-Ku, Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Chiyoda-Ku, Tokyo
- 代理机构: Buchanan Ingersoll & Rooney PC
- 优先权: JP2004-132748 20040428
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.
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