发明授权
US07421053B1 Fast clock acquisition enable method using phase stir injection to PLL for burst mode optical receivers
失效
快速时钟采集启用方法,使用相位搅拌注入到突发模式光接收器的PLL
- 专利标题: Fast clock acquisition enable method using phase stir injection to PLL for burst mode optical receivers
- 专利标题(中): 快速时钟采集启用方法,使用相位搅拌注入到突发模式光接收器的PLL
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申请号: US10423819申请日: 2003-04-25
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公开(公告)号: US07421053B1公开(公告)日: 2008-09-02
- 发明人: Bing Li , David Wolf , James Plesa , Lakshman S. Tamil
- 申请人: Bing Li , David Wolf , James Plesa , Lakshman S. Tamil
- 申请人地址: US DE Wilmington
- 专利权人: YT Networks Capital, LLC
- 当前专利权人: YT Networks Capital, LLC
- 当前专利权人地址: US DE Wilmington
- 代理机构: Connolly Bove Lodge & Hutz LLP
- 主分类号: H03D3/24
- IPC分类号: H03D3/24
摘要:
Systems and methods for aligning the phase of a PLL with an incoming data signal. In one embodiment, when a data signal is received in a PLL, a phase perturbation signal is generated and injected into the PLL. The PLL then performs a phase alignment procedure to lock on to the received data signal. The phase perturbation signal is a damped sinusoidal oscillation that is injected into the PLL when each of a plurality of data packets is received. The perturbation signal has an amplitude sufficient to bump the PLL out of a quasi-stable state around 180 degrees out of phase with the incoming data signal, but is damped to less than a degree of phase shift within 30 ns of being injected.
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