Fast clock acquisition enable method using phase stir injection to PLL for burst mode optical receivers
    1.
    发明授权
    Fast clock acquisition enable method using phase stir injection to PLL for burst mode optical receivers 失效
    快速时钟采集启用方法,使用相位搅拌注入到突发模式光接收器的PLL

    公开(公告)号:US07421053B1

    公开(公告)日:2008-09-02

    申请号:US10423819

    申请日:2003-04-25

    IPC分类号: H03D3/24

    摘要: Systems and methods for aligning the phase of a PLL with an incoming data signal. In one embodiment, when a data signal is received in a PLL, a phase perturbation signal is generated and injected into the PLL. The PLL then performs a phase alignment procedure to lock on to the received data signal. The phase perturbation signal is a damped sinusoidal oscillation that is injected into the PLL when each of a plurality of data packets is received. The perturbation signal has an amplitude sufficient to bump the PLL out of a quasi-stable state around 180 degrees out of phase with the incoming data signal, but is damped to less than a degree of phase shift within 30 ns of being injected.

    摘要翻译: 用于使PLL的相位与输入数据信号对准的系统和方法。 在一个实施例中,当在PLL中接收到数据信号时,产生相位扰动信号并将其注入到PLL中。 PLL然后执行相位对准过程以锁定到接收的数据信号。 相位扰动信号是在接收到多个数据分组中的每一个时被注入到PLL中的阻尼正弦振荡。 扰动信号具有足够的振幅,使PLL能够与进入的数据信号相差180度的准稳态,使其相位不同,但在被注入的30ns内被阻尼到小于一个相位程度。

    System and method for fast dynamic adjustment of slicing level for burst mode optical receivers
    2.
    发明授权
    System and method for fast dynamic adjustment of slicing level for burst mode optical receivers 失效
    用于突发模式光接收机的限幅电平快速动态调整的系统和方法

    公开(公告)号:US07729453B1

    公开(公告)日:2010-06-01

    申请号:US10423480

    申请日:2003-04-25

    IPC分类号: H04L25/10

    摘要: Systems and methods for determining a slicing level which is used as a threshold to determine whether timeslots of an incoming data signal contain ones or zeros. The method of one embodiment comprises receiving a data signal, identifying a maximum level of the data signal, identifying a minimum level of the data signal, determining an average of the minimum and maximum levels, and then using the average of the minimum and maximum levels as a slicing level to identify bits of a data packet embodied in the data signal.

    摘要翻译: 用于确定限制电平的系统和方法,其用作阈值以确定输入数据信号的时隙是否包含1或零。 一个实施例的方法包括接收数据信号,识别数据信号的最大电平,识别数据信号的最小电平,确定最小和最大电平的平均值,然后使用最小和最大电平的平均值 作为用于标识数据信号中体现的数据包的位的限幅电平。