发明授权
US07421525B2 System including a host connected to a plurality of memory modules via a serial memory interconnect
有权
系统包括通过串行存储器互连连接到多个存储器模块的主机
- 专利标题： System including a host connected to a plurality of memory modules via a serial memory interconnect
- 专利标题（中）： 系统包括通过串行存储器互连连接到多个存储器模块的主机
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申请号： US10842296申请日： 2004-05-10
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公开(公告)号： US07421525B2公开(公告)日： 2008-09-02
- 发明人: R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
- 申请人： R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
- 申请人地址： US TX Austin
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US TX Austin
- 代理机构： Ingrassia Fisher & Lorenz, P.C.
- 主分类号： G06F13/00
- IPC分类号： G06F13/00 ; G06F13/28 ; G06F12/00 ; G11C5/06
摘要：
A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
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