Invention Grant
- Patent Title: In-situ deposition for cu hillock suppression
- Patent Title (中): 原位沉积用于小丘抑制
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Application No.: US11334849Application Date: 2006-01-19
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Publication No.: US07423347B2Publication Date: 2008-09-09
- Inventor: Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
- Applicant: Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.
Public/Granted literature
- US20070164439A1 In-situ deposition for cu hillock suppression Public/Granted day:2007-07-19
Information query
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