发明授权
- 专利标题: Device with self aligned gaps for capacitance reduction
- 专利标题(中): 具有自对准间隙的器件,用于降低电容
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申请号: US11291672申请日: 2005-11-30
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公开(公告)号: US07432189B2公开(公告)日: 2008-10-07
- 发明人: S. M. Reza Sadjadi , Zhi-Song Huang
- 申请人: S. M. Reza Sadjadi , Zhi-Song Huang
- 申请人地址: US CA Fremont
- 专利权人: Lam Research Corporation
- 当前专利权人: Lam Research Corporation
- 当前专利权人地址: US CA Fremont
- 代理机构: Beyer Law Group LLP
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
公开/授权文献
- US20070123017A1 Device with self aligned gaps for capacitance reduction 公开/授权日:2007-05-31