Invention Grant
- Patent Title: Semiconductor package and fabrication process thereof
- Patent Title (中): 半导体封装及其制造工艺
-
Application No.: US11544934Application Date: 2006-10-10
-
Publication No.: US07432601B2Publication Date: 2008-10-07
- Inventor: Cheng-Pin Chen
- Applicant: Cheng-Pin Chen
- Applicant Address: TW Hsinchu
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Troxell Law Office, PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.
Public/Granted literature
- US20080093748A1 Semiconductor package and fabrication process thereof Public/Granted day:2008-04-24
Information query
IPC分类: