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公开(公告)号：US11990494B2
公开(公告)日：2024-05-21
申请号：US17383376
申请日：2021-07-22
IPC分类号： H01L27/146
CPC分类号： H01L27/14634 , H01L27/14618 , H01L27/1462 , H01L27/14632 , H01L27/14636 , H01L27/14643 , H01L27/14685 , H01L27/14687 , H01L27/14689 , H01L27/1469
摘要： A package structure including a first die, a second die, an encapsulant, a dam structure, a light-transmitting sheet, a conductive connector, a circuit layer, and a conductive terminal is provided. The first die includes a first active surface. The first active surface has a sensing area. The second die is arranged such that a second back surface thereof faces the first die. The encapsulant covers the second die. The encapsulant has a first encapsulating surface and a second encapsulating surface. The dam structure is located on the first encapsulating surface and exposes the sensing area. The light-transmitting sheet is located on the dam structure. The conductive connector penetrates the encapsulant. The circuit layer is located on the second encapsulating surface. The first die is electrically connected to the second die through the conductive connector and the circuit layer. The conductive terminal is disposed on the circuit layer.
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公开(公告)号：US11916035B2
公开(公告)日：2024-02-27
申请号：US17392274
申请日：2021-08-03
IPC分类号： H01L23/00 , H01L23/48 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L24/73 , H01L24/19 , H01L24/20 , H01L24/26 , H01L24/96 , H01L25/0652 , H01L25/18 , H01L25/50 , H01L23/481 , H01L24/16 , H01L24/24 , H01L24/32 , H01L2224/16145 , H01L2224/2101 , H01L2224/221 , H01L2224/24146 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2224/73209 , H01L2224/73217
摘要： A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.
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公开(公告)号：US20240021595A1
公开(公告)日：2024-01-18
申请号：US18209500
申请日：2023-06-14
IPC分类号： H01L25/16 , H01L23/538 , H01L23/48 , H01L23/498 , H01L21/48 , H01L21/56
CPC分类号： H01L25/167 , H01L23/5385 , H01L23/5389 , H01L23/5383 , H01L23/481 , H01L23/49816 , H01L21/4857 , H01L21/56 , H01L2224/16225 , H01L24/16
摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a first package and a second package, and the second package is disposed on the first package. The first package includes a first redistribution layer, at least one chip and a second redistribution layer. The chip is disposed between the first redistribution layer and the second redistribution layer. The second package includes a third redistribution layer and at least three light-emitting elements. The third redistribution layer is electrically connected to the second redistribution layer, and the second redistribution layer is disposed between the chip and the third redistribution layer. The light-emitting elements are disposed on the third redistribution layer and electrically connected to the third redistribution layer. Each light-emitting element includes a first surface opposite to the third redistribution layer, and the first surfaces of the light-emitting elements are coplanar.
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公开(公告)号：US11848318B2
公开(公告)日：2023-12-19
申请号：US17407174
申请日：2021-08-19
发明人： Pei-Hsun Chou , Ko-Lun Liao
CPC分类号： H01L25/18 , H01L21/561 , H01L23/3128 , H01L23/3135 , H01L24/32 , H01L2224/32145 , H01L2224/32225
摘要： A package structure and a manufacturing thereof are provided. The package structure includes a base, a chip, a control element and an underfill. The chip is disposed on the base and includes a recess, and the recess has a bottom surface and a sidewall. The control element is disposed between the base and the chip and disposed on the bottom surface of the recess, and a gap exists between the control element and the sidewall of the recess. The underfill is disposed in the recess. The chip and the control element are electrically connected to the base respectively.
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公开(公告)号：US20230223311A1
公开(公告)日：2023-07-13
申请号：US17840209
申请日：2022-06-14
发明人： Kun-Yung HUANG , Jen-I HUANG
CPC分类号： H01L23/3192 , H01L24/05 , H01L2224/02371 , H01L2224/0239 , H01L2224/02331
摘要： A semiconductor packaging assembly includes a redistribution layered structure having a plurality of device regions and a plurality of cutting regions separating the device regions, a plurality of recess structures respectively formed in the cutting regions, a plurality of chips respectively disposed in the device regions, and an encapsulating layer formed on the redistribution layered structure to fill the recess structures and enclose the chips.
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公开(公告)号：US11658084B2
公开(公告)日：2023-05-23
申请号：US17318066
申请日：2021-05-12
发明人： Shun-Ming Yu , Han-Ming Chu
CPC分类号： H01L23/3121 , H01L21/565
摘要： A semiconductor packaging structure includes a substrate, a wiring layer, a mask layer, and a sealing layer. The substrate has an effective region and a dummy region surrounding the effective region. The wiring layer is disposed on the effective and dummy regions, and is formed with a predetermined pattern including spaced-apart protrusions to define at least one cavity partially exposing the dummy region. The mask layer covers the wiring layer, and is formed with a through hole to communicate in space with the cavity. The through hole is smaller in size than the cavity, and cooperates with the cavity to form an accommodating space. The sealing layer covers the mask layer, and includes an engaging element filling the accommodating space and adhering to the substrate.
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公开(公告)号：US11557533B2
公开(公告)日：2023-01-17
申请号：US17080853
申请日：2020-10-27
发明人： Hung-Hsin Hsu , Nan-Chun Lin
IPC分类号： H01L21/48 , H01L23/498 , H01L23/00 , H01L25/18 , H01L21/56 , H01L21/683 , H01L25/065 , H01L25/16 , H01L25/00 , H01L23/31 , H01L23/538 , H01L23/24 , H01L21/78 , H01L23/16 , H01L23/367 , H01L23/552
摘要： A package structure including a redistribution circuit structure, a first chip, a second chip, a first circuit board, a second circuit board, and a plurality of conductive terminals is provided. The redistribution circuit structure has a first connection surface and a second connection surface opposite to the first connection surface. The first chip and the second chip are disposed on the first connection surface and are electrically connected to the redistribution circuit structure. The first circuit board and the second circuit board are disposed on the second connection surface and are electrically connected to the redistribution circuit structure. The conductive terminals are disposed on the first circuit board or the second circuit board. The conductive terminals are electrically connected to the first circuit board or the second circuit board. A manufacturing method of a package structure is also provided.
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公开(公告)号：US11456243B2
公开(公告)日：2022-09-27
申请号：US17080859
申请日：2020-10-27
IPC分类号： H01L23/498 , H01L23/00 , H01L25/18 , H01L21/56 , H01L21/683 , H01L25/065 , H01L25/16 , H01L25/00 , H01L23/31 , H01L23/538 , H01L21/48 , H01L23/24 , H01L21/78 , H01L23/16 , H01L23/367 , H01L23/552
摘要： A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.
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公开(公告)号：US20220165709A1
公开(公告)日：2022-05-26
申请号：US17210452
申请日：2021-03-23
发明人： Yin-Huang KUNG , Chia-Hung LIN , Fu-Yuan YAO , Chun-Wu LIU
IPC分类号： H01L25/065 , H01L25/00
摘要： A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.
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公开(公告)号：US20220148955A1
公开(公告)日：2022-05-12
申请号：US17198653
申请日：2021-03-11
发明人： Chih-Yen SU , Chun-Te Lin
IPC分类号： H01L23/498 , H01L23/31 , H01L23/00
摘要： A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.
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