An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a test mode, wherein the error datum is output via a first and a second data output, and wherein an address and a read command are applied to the integrated circuit to read out the error datum associated with the address via one of the data outputs. The test circuit is configured in such a manner that, when a first read command is applied, the test circuit outputs the error datum at the first data output and switches the second data output to high impedance and, when a second read command is applied, the test circuit outputs the error datum at the second data output and switches the first data output to high impedance.