发明授权
US07435654B2 Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same
有权
具有至少三个高k电介质层的模拟电容器及其制造方法
- 专利标题: Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same
- 专利标题(中): 具有至少三个高k电介质层的模拟电容器及其制造方法
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申请号: US11452828申请日: 2006-06-14
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公开(公告)号: US07435654B2公开(公告)日: 2008-10-14
- 发明人: Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
- 申请人: Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
- 申请人地址: KR
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Mills & Onello LLP
- 优先权: KR03-65272 20030919
- 主分类号: H01L21/20
- IPC分类号: H01L21/20 ; H01L21/44
摘要:
There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.