公开(公告)号：US07863201B2

公开(公告)日：2011-01-04

申请号：US12402816

申请日：2009-03-12

申请人： Yong-Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

发明人： Yong-Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/00

CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

摘要翻译： 根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。 在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。 通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。 这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。 该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。

公开(公告)号：US07833580B2

公开(公告)日：2010-11-16

申请号：US10859166

申请日：2004-06-03

申请人： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

发明人： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

IPC分类号： C23C18/00 ,  C23C16/26

CPC分类号： C23C16/4554 ,  C23C16/0281 ,  C23C16/26 ,  C30B29/02 ,  C30B29/605

摘要： A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.

摘要翻译： 形成碳纳米材料层的方法可以包括循环沉积技术。 在该方法中，可以在基板上形成化学吸附层或化学气相沉积层。 杂质可以从化学吸附层或化学气相沉积层去除，以在基底上形成碳原子层。 可以通过重复该方法形成多于一个的碳原子层。

公开(公告)号：US07476922B2

公开(公告)日：2009-01-13

申请号：US10969098

申请日：2004-10-20

申请人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

发明人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

摘要： A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

摘要翻译： 在互连层之间具有垂直延伸的MIM电容器的逻辑器件包括半导体衬底。 下部互连层位于半导体衬底上方，并且上互连层位于下互连层上。 U形下金属板插入在下互连层和上互连层之间。 U形下金属板直接接触下互连层。 电容器电介质层覆盖下金属板的内表面。 此外，电容器介电层具有插入在下金属板的边缘和上互连层之间的延伸部分。 上金属板覆盖电容器介电层的内表面。 上金属板与上互连层接触并被电容器电介质层约束。

公开(公告)号：US07316961B2

公开(公告)日：2008-01-08

申请号：US11273504

申请日：2005-11-14

申请人： Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong

发明人： Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong

IPC分类号： H01L21/20

CPC分类号： H01L28/65 ,  H01L21/31111 ,  H01L28/55

摘要： Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not exposed, forming an inter-insulating layer by wet-etching the insulating layer so that a region of the lower electrode corresponding to the capacitor forming region is exposed, and sequentially forming a dielectric layer and an upper electrode on the capacitor forming region to fabricate a capacitor.

摘要翻译： 提供一种制造具有电特性增强的半导体器件的方法。 该方法包括在半导体衬底上顺序地形成下电极和绝缘层，对与电容器形成区相对应的绝缘层的区域进行干蚀刻，使得下电极不被暴露，通过湿法形成绝缘层， 蚀刻绝缘层，使得与电容器形成区域相对应的下电极的区域被暴露，并且在电容器形成区域上依次形成电介质层和上电极以制造电容器。

公开(公告)号：US20070178644A1

公开(公告)日：2007-08-02

申请号：US11698070

申请日：2007-01-26

申请人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

发明人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

IPC分类号： H01L21/336

CPC分类号： H01L21/3212 ,  H01L21/76801 ,  H01L21/7684

摘要： A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

摘要翻译： 提供了当执行金属化学机械抛光（CMP）时具有降低（或最小）腐蚀性能的电介质或绝缘层的半导体器件及其制造方法。 半导体器件可以包括形成在衬底上的栅电极。 第一层间氧化物层可以形成在衬底上和栅电极之间。 可以在第一层间氧化物层上形成比第一层间氧化物层硬的第二层间氧化物层。 可以通过第二层间氧化物层和第一层间氧化物层形成插塞电极。

公开(公告)号：US20060158829A1

公开(公告)日：2006-07-20

申请号：US11335411

申请日：2006-01-19

申请人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

发明人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

IPC分类号： H01G4/20

CPC分类号： H01G4/10 ,  H01G4/20

摘要： Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

公开(公告)号：US08951853B1

公开(公告)日：2015-02-10

申请号：US12659474

申请日：2010-03-10

申请人： Pan-Kwi Park ,  Dong-Suk Shin ,  Yong-Kuk Jeong ,  Dong-Hyun Roh ,  Ha-Jin Lim

发明人： Pan-Kwi Park ,  Dong-Suk Shin ,  Yong-Kuk Jeong ,  Dong-Hyun Roh ,  Ha-Jin Lim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7847

摘要： A method of forming a semiconductor device includes forming a gate electrode and source/drain regions in a semiconductor substrate, forming a first capping nitride layer covering the gate electrode and the source/drain regions, the first capping nitride layer including a Si—H rich SiN layer, annealing the semiconductor substrate having the first capping nitride layer, and removing the first capping nitride layer.

摘要翻译： 形成半导体器件的方法包括在半导体衬底中形成栅电极和源/漏区，形成覆盖栅电极和源/漏区的第一覆盖氮化物层，第一覆盖氮化物层包括富Si-H SiN层，退火具有第一覆盖氮化物层的半导体衬底，以及去除第一覆盖氮化物层。

公开(公告)号：US08361852B2

公开(公告)日：2013-01-29

申请号：US12980519

申请日：2010-12-29

申请人： Yong-Kuk Jeong

发明人： Yong-Kuk Jeong

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66651

摘要： A transistor includes a silicon germanium channel layer formed on a portion of a single crystalline silicon substrate. The silicon germanium channel layer includes a Si—H bond and/or a Ge—H bond at an inner portion or an upper surface portion thereof. A PMOS transistor is provided on the silicon germanium channel layer. A silicon nitride layer is provided on surface portions of the single crystalline silicon substrate, the silicon germanium channel layer and the PMOS transistor for applying a tensile stress. The MOS transistor shows good operating characteristics.

摘要翻译： 晶体管包括形成在单晶硅衬底的一部分上的硅锗沟道层。 硅锗沟道层在其内部或上表面部分包括Si-H键和/或Ge-H键。 PMOS晶体管设置在硅锗沟道层上。 在单晶硅衬底，硅锗沟道层和用于施加拉应力的PMOS晶体管的表面部分上提供氮化硅层。 MOS晶体管表现出良好的工作特性。

公开(公告)号：US20110207273A1

公开(公告)日：2011-08-25

申请号：US12980519

申请日：2010-12-29

申请人： Yong-Kuk Jeong

发明人： Yong-Kuk Jeong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66651

摘要： A transistor includes a silicon germanium channel layer formed on a portion of a single crystalline silicon substrate. The silicon germanium channel layer includes a Si—H bond and/or a Ge—H bond at an inner portion or an upper surface portion thereof. A PMOS transistor is provided on the silicon germanium channel layer. A silicon nitride layer is provided on surface portions of the single crystalline silicon substrate, the silicon germanium channel layer and the PMOS transistor for applying a tensile stress. The MOS transistor shows good operating characteristics.

摘要翻译： 晶体管包括形成在单晶硅衬底的一部分上的硅锗沟道层。 硅锗沟道层在其内部或上表面部分包括Si-H键和/或Ge-H键。 PMOS晶体管设置在硅锗沟道层上。 在单晶硅衬底，硅锗沟道层和用于施加拉应力的PMOS晶体管的表面部分上提供氮化硅层。 MOS晶体管表现出良好的工作特性。

公开(公告)号：US07709927B2

公开(公告)日：2010-05-04

申请号：US12123817

申请日：2008-05-20

申请人： Dong-suk Shin ,  Il-young Yoon ,  Yong-kuk Jeong ,  Jung-shik Heo

发明人： Dong-suk Shin ,  Il-young Yoon ,  Yong-kuk Jeong ,  Jung-shik Heo

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.

摘要翻译： 半导体器件包括覆盖沟槽的内壁，侧壁氧化物层上的氮化物衬垫和填充氮化物衬垫上的沟槽的间隙填充绝缘层的侧壁氧化物层。 第一杂质掺杂氧化物层设置在侧壁氧化物层的两个端部的边缘区域处，以便从邻近衬底的上表面的沟槽的入口延伸到氮化物衬垫。 凹槽填充绝缘层设置在沟槽中的氮化物衬垫上，以保护第一掺杂杂质的氧化物层的表面。 还公开了相关方法。