发明授权
- 专利标题： Trilayer resist scheme for gate etching applications
- 专利标题（中）： 栅极蚀刻应用的三层抗蚀剂方案
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申请号： US11506227申请日： 2006-08-18
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公开(公告)号： US07435671B2公开(公告)日： 2008-10-14
- 发明人: Nicholas C. Fuller , Timothy J. Dalton , Ying Zhang
- 申请人： Nicholas C. Fuller , Timothy J. Dalton , Ying Zhang
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Scully, Scott, Murphy & Presser, P.C.
- 代理商 Robert M. Trepp, Esq.
- 主分类号： H01L21/3205
- IPC分类号： H01L21/3205
摘要：
A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.
公开/授权文献
- US20080045011A1 Trilayer resist scheme for gate etching applications 公开/授权日：2008-02-21
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