公开(公告)号：US07435671B2

公开(公告)日：2008-10-14

申请号：US11506227

申请日：2006-08-18

申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

摘要翻译： 提供三层抗蚀剂（TLR）图案化方案，以使栅极导体，特别是多晶硅栅极导体，临界尺寸（CD）小于40nm，最小LER和LWR。 根据本发明，本发明的图案化方案利用有机/无机/有机多层堆叠代替现有技术中使用的有机层。 本发明TLR的顶部有机层是诸如193nm光致抗蚀剂的光致抗蚀剂材料，其位于抗反射涂层（ARC）的顶部，抗反射涂层也由有机材料构成。 TLR的中间无机层包括任何氧化物层，例如化学气相沉积（CVD）的低温（小于或等于250℃），源自TEOS（原硅酸四乙酯），氧化硅 ，硅烷氧化物或含Si的ARC材料。 TLR的底部有机层包括任何有机层，例如近无摩擦碳（NFC），类金刚石碳，热固性聚亚芳基醚。

公开(公告)号：US08084825B2

公开(公告)日：2011-12-27

申请号：US12245946

申请日：2008-10-06

申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L20/10

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

摘要翻译： 提供三层抗蚀剂（TLR）图案化方案，以使栅极导体，特别是多晶硅栅极导体，临界尺寸（CD）小于40nm，最小LER和LWR。 根据本发明，本发明的图案化方案利用有机/无机/有机多层堆叠代替现有技术中使用的有机层。 本发明TLR的顶部有机层是诸如193nm光致抗蚀剂的光致抗蚀剂材料，其位于抗反射涂层（ARC）的顶部，抗反射涂层也由有机材料构成。 TLR的中间无机层包括任何氧化物层，例如化学气相沉积（CVD）的低温（小于或等于250℃），源自TEOS（原硅酸四乙酯），氧化硅 ，硅烷氧化物或含Si的ARC材料。 TLR的底部有机层包括任何有机层，例如近无摩擦碳（NFC），类金刚石碳，热固性聚亚芳基醚。

公开(公告)号：US20080045011A1

公开(公告)日：2008-02-21

申请号：US11506227

申请日：2006-08-18

申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

公开(公告)号：US20090101985A1

公开(公告)日：2009-04-23

申请号：US12245946

申请日：2008-10-06

申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/10

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

摘要翻译： 提供三层抗蚀剂（TLR）图案化方案，以使栅极导体，特别是多晶硅栅极导体，临界尺寸（CD）小于40nm，最小LER和LWR。 根据本发明，本发明的图案化方案利用有机/无机/有机多层堆叠代替现有技术中使用的有机层。 本发明TLR的顶部有机层是诸如193nm光致抗蚀剂的光致抗蚀剂材料，其位于抗反射涂层（ARC）的顶部，抗反射涂层也由有机材料构成。 TLR的中间无机层包括任何氧化物层，例如化学气相沉积（CVD）的低温（小于或等于250℃），源自TEOS（原硅酸四乙酯），氧化硅 ，硅烷氧化物或含Si的ARC材料。 TLR的底部有机层包括任何有机层，例如近无摩擦碳（NFC），类金刚石碳，热固性聚亚芳基醚。

公开(公告)号：US20110278580A1

公开(公告)日：2011-11-17

申请号：US12779079

申请日：2010-05-13

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L21/311

CPC分类号： H01L29/78675 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

摘要： A method for fabricating recessed source regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造积极缩放CMOS器件的凹陷源区的方法。 在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控制地在薄体的沟道中形成远远小于40nm的器件的源极的凹陷区域，以使SiGe，SiC的后续外延生长 ，或其他材料，并且随之而来的器件和环形振荡器性能的增加。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US08716798B2

公开(公告)日：2014-05-06

申请号：US12779100

申请日：2010-05-13

申请人： Nicholas C Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L27/12

CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US20120305928A1

公开(公告)日：2012-12-06

申请号：US13565035

申请日：2012-08-02

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/786

CPC分类号： H01L29/78675 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

摘要： A Field Effect Transistor (FET) device includes a gate stack formed over a channel region, a source region adjacent to the channel region, wherein a portion of a boundary between the source region and the channel region is defined along a plane defined by a sidewall of the gate stack, a drain region adjacent to the channel region, a portion of the drain region arranged below the gate stack, a native oxide layer disposed over a portion of the source region, along sidewalls of the gate stack, and over a portion of the drain region, a spacer arranged over a portion of the native oxide layer above the source region and the drain region and along the native oxide layer along the sidewalls of the gate stack.

摘要翻译： 场效应晶体管（FET）器件包括形成在通道区域上的栅极堆叠，与沟道区域相邻的源极区域，其中源极区域和沟道区域之间的边界的一部分沿着由侧壁 栅极堆叠的漏极区域，与沟道区域相邻的漏极区域，布置在栅极堆叠下方的漏极区域的一部分，沿着栅极堆叠的侧壁设置在源极区域的一部分上的自然氧化物层， 漏极区域上的间隔物，其间隔设置在源极区域和漏极区域上方的自然氧化物层的一部分上，并且沿着栅极叠层的侧壁沿着天然氧化物层。

公开(公告)号：US20110278673A1

公开(公告)日：2011-11-17

申请号：US12779100

申请日：2010-05-13

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/786 ,  H01L21/306

CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US20130012026A1

公开(公告)日：2013-01-10

申请号：US13611678

申请日：2012-09-12

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L21/311

CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US20110278672A1

公开(公告)日：2011-11-17

申请号：US12779087

申请日：2010-05-13

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L21/302

CPC分类号： H01L27/092 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66757

摘要： A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造积极缩放的CMOS器件的凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控地形成薄体的沟道中的漏极的凹陷区域，远小于40nm的器件，以使SiGe，SiC的后续外延生长 ，或其他材料，并且随之而来的器件和环形振荡器性能的增加。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向异性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。