Invention Grant
US07436043B2 N-well and N+ buried layer isolation by auto doping to reduce chip size
有权
N阱和N +埋层隔离通过自动掺杂减少芯片尺寸
- Patent Title: N-well and N+ buried layer isolation by auto doping to reduce chip size
- Patent Title (中): N阱和N +埋层隔离通过自动掺杂减少芯片尺寸
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Application No.: US11019753Application Date: 2004-12-21
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Publication No.: US07436043B2Publication Date: 2008-10-14
- Inventor: Tzu-Chiang Sung , Chih Po Huang , Rann Shyan Yeh , Jun Xiu Liu , Chi-Hsuen Chang , Chung-I Chen
- Applicant: Tzu-Chiang Sung , Chih Po Huang , Rann Shyan Yeh , Jun Xiu Liu , Chi-Hsuen Chang , Chung-I Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L21/74
- IPC: H01L21/74

Abstract:
A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.
Public/Granted literature
- US20060133189A1 N-well and N+ buried layer isolation by auto doping to reduce chip size Public/Granted day:2006-06-22
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