Invention Grant
US07436043B2 N-well and N+ buried layer isolation by auto doping to reduce chip size 有权
N阱和N +埋层隔离通过自动掺杂减少芯片尺寸

N-well and N+ buried layer isolation by auto doping to reduce chip size
Abstract:
A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.
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