公开(公告)号：US07521741B2

公开(公告)日：2009-04-21

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US20080001189A1

公开(公告)日：2008-01-03

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US20070235831A1

公开(公告)日：2007-10-11

申请号：US11273228

申请日：2005-11-12

申请人： Chia-Wei Liu ,  Jun Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

发明人： Chia-Wei Liu ,  Jun Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L27/088

摘要： A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

摘要翻译： 用于隔离各种工作电压的第一电路和第二电路的半导体结构包括围绕半导体衬底上的第一和第二电路的第一隔离环。 在第一和第二电路下连续延伸的掩埋层形成在半导体衬底上，其中掩埋层与第一隔离环接合，用于将第一和第二电路与半导体衬底的背面偏置隔离。 离子增强隔离层介于掩埋层和形成有第一和第二电路的器件的阱区之间，其中离子增强隔离层掺杂了与掩埋层不同的极性类型的杂质。

公开(公告)号：US07196392B2

公开(公告)日：2007-03-27

申请号：US11136810

申请日：2005-05-24

申请人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Po Huang

发明人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Po Huang

IPC分类号： H01L29/00

CPC分类号： H01L21/761 ,  H01L21/76232 ,  H01L27/088 ,  H01L27/0921

摘要： A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.

摘要翻译： 半导体结构包括设置在半导体衬底上的隔离环，围绕第一和第二电路区域。 掩埋隔离层在半导体衬底中连续延伸穿过第一电路区域和第二电路区域。 掩埋隔离层与隔离环接合，从而将第一和第二电路区域与半导体衬底的背面偏置隔离。 离子增强隔离层将第一电路区域中的第一阱和第二电路区域中的第二阱与隔离环和掩埋隔离层分离，从而防止电路区域的阱和掩埋隔离层之间的穿通 。

公开(公告)号：US20060211190A1

公开(公告)日：2006-09-21

申请号：US11082514

申请日：2005-03-16

申请人： Chien-Mao Chen ,  Jun Liu ,  Cuker Huang ,  Chi-Hsuen Chang

发明人： Chien-Mao Chen ,  Jun Liu ,  Cuker Huang ,  Chi-Hsuen Chang

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823481 ,  H01L21/823462 ,  Y10S438/942

摘要： A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.

摘要翻译： 在相同的集成电路器件中提供了一种用于形成具有不同栅极氧化物厚度和不同相关工作电压的至少三个器件的方法。 该方法包括在同一集成电路器件中在高电压和低电压区域形成具有不同厚度的多个栅极氧化物。 使用干蚀刻操作，使用低电压区域的光掩模和高电压区域中的硬掩模从高电压区域去除相对厚的栅极氧化物，以掩蔽栅极氧化物膜。 然后使用湿蚀刻步骤从低电压区域去除栅氧化膜。 硬掩模可以形成在多晶硅结构上。

公开(公告)号：US20060113571A1

公开(公告)日：2006-06-01

申请号：US11136810

申请日：2005-05-24

申请人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Huang

发明人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Huang

IPC分类号： H01L29/768

CPC分类号： H01L21/761 ,  H01L21/76232 ,  H01L27/088 ,  H01L27/0921

摘要： A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.

摘要翻译： 半导体结构包括设置在半导体衬底上的隔离环，围绕第一和第二电路区域。 掩埋隔离层在半导体衬底中连续延伸穿过第一电路区域和第二电路区域。 掩埋隔离层与隔离环接合，从而将第一和第二电路区域与半导体衬底的背面偏置隔离。 离子增强隔离层将第一电路区域中的第一阱和第二电路区域中的第二阱与隔离环和掩埋隔离层分离，从而防止电路区域的阱和掩埋隔离层之间的穿通 。

公开(公告)号：US20060113627A1

公开(公告)日：2006-06-01

申请号：US10999508

申请日：2004-11-29

申请人： Chung-I Chen ,  Hsin Kuan ,  Zhi-Cheng Chen ,  Rann-Shyan Yeh ,  Chi-Hsuen Chang ,  Jun Liu ,  Tzu-Chiang Sung ,  Chia-Wei Liu ,  Jieh-Ting Chang

发明人： Chung-I Chen ,  Hsin Kuan ,  Zhi-Cheng Chen ,  Rann-Shyan Yeh ,  Chi-Hsuen Chang ,  Jun Liu ,  Tzu-Chiang Sung ,  Chia-Wei Liu ,  Jieh-Ting Chang

IPC分类号： H01L29/00

CPC分类号： H01L29/7835 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

摘要翻译： 提供了一种用于后续接触孔工艺的具有层间电介质（ILD）蚀刻停止层的高压晶体管器件。 蚀刻停止层是具有大于10欧姆 - 厘米电阻率的高电阻率薄膜，因此在栅极处驱动大于5V的高电压时，可以防止泄漏并提高击穿电压。 制造高压器件的方法与当前的低压器件工艺和中压器件工艺兼容。

公开(公告)号：US07301185B2

公开(公告)日：2007-11-27

申请号：US10999508

申请日：2004-11-29

申请人： Chung-I Chen ,  Hsin Kuan ,  Zhi-Cheng Chen ,  Rann-Shyan Yeh ,  Chi-Hsuen Chang ,  Jun Xiu Liu ,  Tzu-Chiang Sung ,  Chia-Wei Liu ,  Jieh-Ting Cheng

发明人： Chung-I Chen ,  Hsin Kuan ,  Zhi-Cheng Chen ,  Rann-Shyan Yeh ,  Chi-Hsuen Chang ,  Jun Xiu Liu ,  Tzu-Chiang Sung ,  Chia-Wei Liu ,  Jieh-Ting Cheng

IPC分类号： H01L27/148 ,  H01L29/80 ,  H01L21/824

CPC分类号： H01L29/7835 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

摘要翻译： 提供了一种用于后续接触孔工艺的具有层间电介质（ILD）蚀刻停止层的高压晶体管器件。 蚀刻停止层是具有大于10欧姆 - 厘米电阻率的高电阻率薄膜，因此在栅极处驱动大于5V的高电压时，可以防止泄漏并提高击穿电压。 制造高压器件的方法与当前的低压器件工艺和中压器件工艺兼容。

公开(公告)号：US07253114B2

公开(公告)日：2007-08-07

申请号：US11082514

申请日：2005-03-16

申请人： Chien-Mao Chen ,  Jun Xiu Liu ,  Cuker Huang ,  Chi-Hsuen Chang

发明人： Chien-Mao Chen ,  Jun Xiu Liu ,  Cuker Huang ,  Chi-Hsuen Chang

IPC分类号： H01L21/302

CPC分类号： H01L21/823481 ,  H01L21/823462 ,  Y10S438/942

摘要： A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.

摘要翻译： 在相同的集成电路器件中提供了一种用于形成具有不同栅极氧化物厚度和不同相关工作电压的至少三个器件的方法。 该方法包括在同一集成电路器件中在高电压和低电压区域形成具有不同厚度的多个栅极氧化物。 使用干蚀刻操作，使用低电压区域的光掩模和高电压区域中的硬掩模从高电压区域去除相对厚的栅极氧化物，以掩蔽栅极氧化物膜。 然后使用湿蚀刻步骤从低电压区域去除栅氧化膜。 硬掩模可以形成在多晶硅结构上。

公开(公告)号：US20060006462A1

公开(公告)日：2006-01-12

申请号：US11122635

申请日：2005-05-05

申请人： Chi-Hsuen Chang ,  Jun Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Huang ,  Rann Yeh

发明人： Chi-Hsuen Chang ,  Jun Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Huang ,  Rann Yeh

IPC分类号： H01L29/76

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7816

摘要： Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.

摘要翻译： 描述了包括高压MOS晶体管的半导体器件的方法和装置。 衬底设置有彼此分离的低电压和高电压区域。 形成包含绝缘体的隔离区，包括形成在高电压区域内的所述阱内的至少一个。 从高电压装置区域中的有源区域到隔离区域的转变角度大于预定角度，在一些实施例中，它与垂直方向大于40度。 在一些实施例中，使用浅沟槽隔离技术形成隔离区域。 在替代实施例中，使用通过硅技术的局部氧化形成的场氧化物形成隔离区。