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发明授权
US07443031B2 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 有权
半导体装置的多层布线结构，制造所述多层布线结构体的方法和用于可靠性评价的半导体装置

Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation
摘要：
A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
摘要（中）：

布置具有层叠结构的半导体器件的多层布线结构，以防止由于施加到相对的上部和下部插塞之间的布线区域的应力引起的可靠性降低。 上插头与下插头与布线之间的接触面上的布线之间的接触面的重叠速率小，不产生空隙的程度。 制造多层布线结构，使得在上部和下部插塞之间的布线区域中不包含晶界。 布线材料与上，下插头材料之间的热膨胀系数差异小到不产生空隙的程度。

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