Invention Grant
US07446007B2 Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof 失效
具有抑制凹陷/底切的多层间隔物及其制造方法

Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof
Abstract:
A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
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