Invention Grant
US07446007B2 Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof
失效
具有抑制凹陷/底切的多层间隔物及其制造方法
- Patent Title: Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof
- Patent Title (中): 具有抑制凹陷/底切的多层间隔物及其制造方法
-
Application No.: US11560893Application Date: 2006-11-17
-
Publication No.: US07446007B2Publication Date: 2008-11-04
- Inventor: James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart, III , Dale W. Martin
- Applicant: James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart, III , Dale W. Martin
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent William D. Sabo, Esq.
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
Public/Granted literature
- US20080116493A1 MULTI-LAYER SPACER WITH INHIBITED RECESS/UNDERCUT AND METHOD FOR FABRICATION THEREOF Public/Granted day:2008-05-22
Information query
IPC分类: