Invention Grant
- Patent Title: Logical operation circuit and logical operation method
- Patent Title (中): 逻辑运算电路及逻辑运算方式
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Application No.: US10502265Application Date: 2003-01-22
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Publication No.: US07450412B2Publication Date: 2008-11-11
- Inventor: Michitaka Kameyama , Takahiro Hanyu , Hiromitsu Kimura , Yoshikazu Fujimori , Takashi Nakamura , Hidemi Takasu
- Applicant: Michitaka Kameyama , Takahiro Hanyu , Hiromitsu Kimura , Yoshikazu Fujimori , Takashi Nakamura , Hidemi Takasu
- Applicant Address: JP Kyoto
- Assignee: Rohm Co., Ltd.
- Current Assignee: Rohm Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Hogan & Hartson LLP
- Priority: JP2002-018661 20020128
- International Application: PCT/JP03/00568 WO 20030122
- International Announcement: WO03/065582 WO 20030807
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
To provide a logical operation circuit which can perform a logical operation using a ferroelectric capacitor and a logical operation method. A logical operation circuit 1 has a ferroelectric capacitors CF and a transistor MP. The ferroelectric capacitor CF can retain a polarization state P1 (y=1) or P2 (y=0) corresponding to first operation target data y. In an operation process, a first terminal 3 of the ferroelectric capacitor 1 is precharged to a source potential Vdd, and a potential corresponding to second operation target data x, that is, a ground potential GND (x=1) or the source potential Vdd (x=0), is given to a second terminal 5 of the ferroelectric capacitor via a bit line BL. When the threshold voltage Vth of the transistor MP is set properly, the transistor MP becomes on or off (on, on, on, off) depending on the combination of x and y (0-0, 0-1, 1-0, 1-1).
Public/Granted literature
- US20050146922A1 Logical operation circuit and logical operation method Public/Granted day:2005-07-07
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