发明授权
US07451295B2 Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues
有权
数据缓存的早期数据返回指示机制，通过调度，重新安排和重播请求队列中的请求，通过早期数据就绪指示来检测数据的准备
- 专利标题： Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues
- 专利标题（中）： 数据缓存的早期数据返回指示机制，通过调度，重新安排和重播请求队列中的请求，通过早期数据就绪指示来检测数据的准备
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申请号： US11541289申请日： 2006-09-28
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公开(公告)号： US07451295B2公开(公告)日： 2008-11-11
- 发明人: Belliappa Kuttanna , Robert G. Milstrey , Stanley J. Domen , Glenn Hinton
- 申请人： Belliappa Kuttanna , Robert G. Milstrey , Stanley J. Domen , Glenn Hinton
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06F12/00
摘要：
One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.
公开/授权文献
- US20070028048A1 Early data return indication mechanism 公开/授权日：2007-02-01
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