发明授权
- 专利标题: Delay locked loop
- 专利标题(中): 延迟锁定环路
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申请号: US10266296申请日: 2002-10-08
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公开(公告)号: US07457392B2公开(公告)日: 2008-11-25
- 发明人: Christian Weis , Thomas Miller , Patrick Heyne
- 申请人: Christian Weis , Thomas Miller , Patrick Heyne
- 申请人地址: DE Munich
- 专利权人: Infineon Technologies AG
- 当前专利权人: Infineon Technologies AG
- 当前专利权人地址: DE Munich
- 代理商 Laurence A. Greenberg; Werner H. Stemer; Ralph E. Locher
- 优先权: DE10149584 20011008
- 主分类号: H03D3/24
- IPC分类号: H03D3/24
摘要:
A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals for controlling the respective delay devices are provided by synchronization latches, which receive a clock obtained by the output signal of the first delay device for obtaining the fine setting. The delay locked loop enables a linear operating behavior at a high operating frequency and is particularly suitable when a differential embodiment of the two delay devices is used.
公开/授权文献
- US20030094984A1 Delay locked loop 公开/授权日:2003-05-22
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