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US07457392B2 Delay locked loop 失效
延迟锁定环路

Delay locked loop
摘要:
A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals for controlling the respective delay devices are provided by synchronization latches, which receive a clock obtained by the output signal of the first delay device for obtaining the fine setting. The delay locked loop enables a linear operating behavior at a high operating frequency and is particularly suitable when a differential embodiment of the two delay devices is used.
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