Invention Grant
US07458057B2 Pattern correction method, pattern correction system, mask manufacturing method, semiconductor device manufacturing method, recording medium, and designed pattern
有权
图案校正方法，图案校正系统，掩模制造方法，半导体器件制造方法，记录介质和设计图案
- Patent Title: Pattern correction method, pattern correction system, mask manufacturing method, semiconductor device manufacturing method, recording medium, and designed pattern
- Patent Title (中): 图案校正方法，图案校正系统，掩模制造方法，半导体器件制造方法，记录介质和设计图案
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Application No.: US10882217Application Date: 2004-07-02
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Publication No.: US07458057B2Publication Date: 2008-11-25
- Inventor: Toshiya Kotani
- Applicant: Toshiya Kotani
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2003-190341 20030702
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
According to an aspect of the invention, there is provided a pattern correction method in which a shape of a target pattern is corrected in accordance with an arrangement state between the target pattern configuring a designed pattern and a vicinity pattern disposed in the vicinity of the target pattern, the pattern correction method comprises detecting a first arrangement state between a first predetermined portion of an edge of the target pattern and the vicinity pattern, detecting a second arrangement state between a second predetermined portion of the edge of the target pattern and the vicinity pattern, determining a correction value of the edge of the target pattern based on a rule in accordance with the first and second arrangement states, and adding the correction value to the edge of the target pattern.
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