公开(公告)号：US08809072B2

公开(公告)日：2014-08-19

申请号：US13051961

申请日：2011-03-18

申请人： Chikaaki Kodama ,  Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

发明人： Chikaaki Kodama ,  Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G03F1/36

摘要： According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.

摘要翻译： 根据实施例中的子分辨率辅助特征排列方法，选择规则库和模型库中的哪一个被设置为对应于主图案的图案数据上的哪个图案区域作为安排子图形的方法的类型， 分辨率辅助功能，用于提高在基板上形成的主图案的分辨率。 然后，将规则库的子分辨率辅助特征设置在设置为规则库的图案区域中，并且由模型库将子分辨率辅助特征排列在设置为模型库的图案区域中。

公开(公告)号：US08617773B2

公开(公告)日：2013-12-31

申请号：US13239019

申请日：2011-09-21

申请人： Taiga Uno ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Yukiyasu Arisawa

发明人： Taiga Uno ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Yukiyasu Arisawa

IPC分类号： G03F1/44 ,  G03F1/72 ,  G03F1/38

CPC分类号： G03F1/36 ,  G03F1/70 ,  G03F7/70441 ,  G03F7/70941

摘要： In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.

摘要翻译： 在根据实施例的校正掩模图案的方法中，对于布局中的每种类型的图案，计算用于参考闪光值的掩模图案校正量作为参考掩模校正量，以及掩模图案校正的改变量 计算与闪光值的变化量对应的量作为变化量信息。 基于从具有图案的信息提取参考掩模校正量和变化量信息相关联的参考掩模校正量和对应于图案的改变量信息，创建与图案的闪光值相对应的掩模图案 并且基于图案的耀斑值和参考闪光值之间的差异。

公开(公告)号：US08332784B2

公开(公告)日：2012-12-11

申请号：US13285650

申请日：2011-10-31

申请人： Toshiya Kotani

发明人： Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  H01J2237/31769

摘要： A semiconductor device is provided having a physical pattern based on a designed pattern, the designed pattern including a target pattern and a correction pattern designed for a pattern to be formed on a wafer; the target pattern includes a first portion of an edge with a first distance, a second portion of the edge with a second distance, which is different from the first distance, and a third portion of the edge having a first region of the edge with the first distance and a second region of the edge with the second distance; and the correction pattern is added to at least one of the first portion, the second portion, and the third portion such that the first portion, the second portion, and the third portion are caused to differ from one another in dimensions of the designed pattern.

摘要翻译： 提供具有基于设计图案的物理图案的半导体器件，所设计的图案包括针对要在晶片上形成的图案设计的目标图案和校正图案; 目标图案包括具有第一距离的边缘的第一部分，具有第二距离的边缘的第二部分，其不同于第一距离，并且边缘的第三部分具有边缘的第一区域，其具有 第一距离和具有第二距离的边缘的第二区域; 并且将修正图案添加到第一部分，第二部分和第三部分中的至少一个，使得第一部分，第二部分和第三部分在设计图案的尺寸上彼此不同 。

公开(公告)号：US20120241834A1

公开(公告)日：2012-09-27

申请号：US13234052

申请日：2011-09-15

申请人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

发明人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/768 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

摘要： According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

摘要翻译： 根据一个实施例，半导体器件包括从元件形成区域延伸到绘图区域并且与元件形成区域中的半导体元件连接并且与绘图区域中的触点连接的互连。 基于在牺牲层的侧表面上匹配第n个（其中n是1或更大的整数）的第一侧壁膜的图案的第（n + 1）第二侧壁膜的图案形成互连。 当曝光装置的曝光波长为λ时，在元件形成区域中匹配互连的互连宽度的第一尺寸和元件形成区域中的互连间隔为（k1 / 2n）×（λ/ NA）或更小，透镜的数值孔径 的曝光装置为NA，处理参数为k1。 在绘图区域中匹配互连间隔的第二维大于第一维度。

公开(公告)号：US08196071B2

公开(公告)日：2012-06-05

申请号：US12688644

申请日：2010-01-15

申请人： Hiromitsu Mashita ,  Katsumi Iyanagi ,  Takafumi Taguchi ,  Toshiya Kotani ,  Hidefumi Mukai ,  Taiga Uno ,  Takashi Nakazawa

发明人： Hiromitsu Mashita ,  Katsumi Iyanagi ,  Takafumi Taguchi ,  Toshiya Kotani ,  Hidefumi Mukai ,  Taiga Uno ,  Takashi Nakazawa

IPC分类号： G06F17/50

CPC分类号： G03F1/80 ,  G03F1/36 ,  G03F1/54

摘要： A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern.

摘要翻译： 一种图形数据生成方法，包括：参照形成在基板上的第一图案和通过使用第一图案处理基板而形成的第二图案之间的尺寸变化量之间的第一对应关系，以及图案总表面积和 第一图案的图案边界长度; 以及创建用于形成第一图案的图案数据。

公开(公告)号：US08143171B2

公开(公告)日：2012-03-27

申请号：US12403740

申请日：2009-03-13

申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Fumiharu Nakajima ,  Takafumi Taguchi ,  Chikaaki Kodama

发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Fumiharu Nakajima ,  Takafumi Taguchi ,  Chikaaki Kodama

IPC分类号： H01L21/461

CPC分类号： H01L21/0337

摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

摘要翻译： 通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸 在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。

公开(公告)号：US08142961B2

公开(公告)日：2012-03-27

申请号：US12717914

申请日：2010-03-04

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Koji Hashimoto ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Koji Hashimoto ,  Soichi Inoue

IPC分类号： G03F1/00

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.

摘要翻译： 公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件 并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

公开(公告)号：US20110265047A1

公开(公告)日：2011-10-27

申请号：US13067810

申请日：2011-06-28

申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

公开(公告)号：US08042067B2

公开(公告)日：2011-10-18

申请号：US12216220

申请日：2008-07-01

申请人： Ayako Nakano ,  Toshiya Kotani

发明人： Ayako Nakano ,  Toshiya Kotani

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F7/705 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

摘要： A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.

摘要翻译： 公开了一种在半导体衬底上形成期望图案的图案形成方法，其包括提取层的第一图案，提取与所述层重叠的一个或多个层的第二图案，所述第二图案被布置成与所述图案重叠或重叠 考虑到预定的处理变化，计算半导体衬底上的第一和第二图案之间的距离，确定第一和第二图案之间的距离是否满足给定的第一和第二图案之间的距离的允许余量 模式，并且如果距离不满足允许余量，则校正第一和第二图案中的至少一个以满足允许余量。

公开(公告)号：USRE42302E1

公开(公告)日：2011-04-19

申请号：US11905862

申请日：2007-10-04

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

CPC分类号： G06F17/5081

摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

摘要翻译： 提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案 所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则 预定条件。