发明授权
- 专利标题： Interconnect structures with surfaces roughness improving liner and methods for fabricating the same
- 专利标题（中）： 互连结构与表面粗糙度改善衬垫及其制造方法
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申请号： US11531304申请日： 2006-09-13
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公开(公告)号： US07466027B2公开(公告)日： 2008-12-16
- 发明人: Chung-Chi Ko , Keng-Chu Lin , Chia-Cheng Chou
- 申请人： Chung-Chi Ko , Keng-Chu Lin , Chia-Cheng Chou
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Thomas, Kayden, Horstemeyer & Risley
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L21/4763
摘要：
Interconnect structures are provided. An exemplary embodiment of an interconnect structure comprises a substrate with a low-k dielectric layer thereon. A via opening and a trench opening are formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and the via opening exposes a portion of the substrate. A liner layer is formed on sidewalls of the low-k dielectric layer exposed by the trench and via protions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via protions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials. A conformal conductive barrier layer is formed in the trench and via openings, covering the liner layer and the exposed portion of the substrate. A conductive layer is formed on the conductive barrier layer, filling in the trench and via openings.
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