The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.